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document no. u15947ej1v1ud00 (1st edition) date published july 2002 n cp(k) printed in japan ? 2002 pd780143 pd780144 pd780146 pd780148 pd78f0148 78k0/kf1 8-bit single-chip microcontrollers preliminary user?s manual
preliminary user?s manual u15947ej1v1ud 2 [memo]
preliminary user?s manual u15947ej1v1ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. ethernet is a trademark of xerox corp. osf/motif is a trademark of open software foundation, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron.
preliminary user ? s manual u15947ej1v1ud 4 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: pd78f0148 the customer must judge the need for a license: pd780143, 780144, 780146, and 780148 ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user ? s manual u15947ej1v1ud 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
preliminary user?s manual u15947ej1v1ud 6 major revisions in this edition page description p.73 p.74 p.76 modification of reset value of the following registers in table 3-5 special function register list serial i/o shift register 10 (sio10) serial i/o shift register 11 (sio11) interrupt mask flag register 1h (mk1h) p.75 modification of manipulatable bit unit of the following register in table 3-5 special function register list oscillation stabilization time counter status register (ostc) p.139 modification of manipulatable bit unit and clear condition in 6.3 (5) oscillation stabilization time counter status register (ostc) pp.146 to 149 modification of figure 6-13 status transition diagram p.150 modification of table 6-4 oscillation control flags and clock oscillation status p.162 modification of reset value in 7.2 (2) 16-bit timer capture/compare register 00n (cr00n) and (3) 16-bit timer capture/compare register 01n (cr01n) p.170 modification of manipulatable bit unit in 7.3 (4) prescaler mode register 0n (prm0n) p.276 addition of caution description in 13.6 (10) a/d conversion result register (adcr) read operation p.347 modification of reset value in 16.2 (2) serial i/o shift register 1n (sio1n) p.435 modification of reset value in 19.3 (2) interrupt mask flag register (mk1h) p.450 modification of manipulatable bit unit and clear condition in 21.1.2 (1) oscillation stabilization time counter status register (ostc) pp.452, 453 modification of a/d converter item in table 21-2 operating statuses in halt mode pp.466, 468 modification of stop condition of clock monitor in 23.1 functions of clock monitor and 23.4 operation of clock monitor pp.474, 475 addition of 24.4 cautions for power-on-clear circuit p.479 modification of figure 25-3 format of low-voltage detection level selection register (lvis) pp.484 to 487 addition of 25.5 cautions for low-voltage detector p.488 modification of description in 26.1 outline of regulator pp.515, 516 p.517 p.518 pp.519 to 522 p.534 p.534 p.535 p.535 p.535 pp.536, 537 modification of the following contents in chapter 30 electrical specifications (target values) ? absolute maximum ratings x1 oscillator characteristics subsystem clock oscillator characteristics dc characteristics a/d converter characteristics poc circuit characteristics lvi circuit characteristics data memory stop mode low supply voltage data retention characteristics (deletion of data retention supply current) deletion of ring-osc characteristics flash memory programming characteristics pp.540 to 542 modification from chapter 32 retry to chapter 32 cautions for wait the mark shows major revised points.
preliminary user?s manual u15947ej1v1ud 7 introduction readers this manual is intended for user engineers who wish to understand the functions of the 78k0/kf1 series and design and develop application systems and programs for these devices. the target products are as follows. 78k0/kf1 series: pd780143, 780144, 780146, 780148, and 78f0148 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/kf1 series manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). 78k0/kf1 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? when using this manual as the manual for (a) products and (a1) products: only the quality grade differs between standard products and (a) and (a1) products. read the part number as follows. ? pd780143 pd780143(a), 780143(a1) ? pd780144 pd780144(a), 780144(a1) ? pd780146 pd780146(a), 780146(a1) ? pd780148 pd780148(a), 780148(a1) ? pd78f0148 pd78f0148(a) ? to gain a general understanding of functions: read this manual in the order of the contents . ? how to interpret the register format: for a bit number enclosed in square, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the c compiler. ? to check the details of a register when you know the register name. refer to appendix c register index .
preliminary user?s manual u15947ej1v1ud 8 ? to know details of the 78k/0 series instructions. refer to the separate document 78k/0 series instructions user?s manual (u12326e) . caution examples in this manual employ the ?standard? quality grade for general electronics. when using examples in this manual for the ?special? quality grade, review the quality grade of each part and/or circuit actually used. conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text. caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/kf1 user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u14445e language u14446e ra78k0 assembler package structured assembly language u11789e operation u14297e cc78k0 c compiler language u14298e sm78k0s, sm78k0 system simulator ver. 2.10 or later operation (windows tm based) u14611e sm78k series system simulator ver. 2.10 or later external part user open interface specifications u15006e id78k0-ns integrated debugger ver. 2.00 or later operation (windows based) u14379e reference u11539e id78k0 integrated debugger windows based guide u11649e fundamentals u11537e rx78k0 real-time os installation u11536e project manager ver. 3.12 or later (windows based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u15947ej1v1ud 9 documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-780148-ns-em1 emulation board to be prepared documents related to flash memory programming document name document no. pg-fp3 flash memory programmer user?s manual u13502e other documents document name document no. semiconductor selection guide ? product & packages ? x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u15947ej1v1ud 10 contents chapter 1 outline........................................................................................................... .................. 28 1.1 features .................................................................................................................. ...................... 28 1.2 applications.............................................................................................................. .................... 29 1.3 ordering information ...................................................................................................... ............. 29 1.4 quality grade............................................................................................................. ................... 32 1.5 pin configuration (top view).............................................................................................. ........ 34 1.6 78k0/kxx series lineup .................................................................................................... .......... 37 1.7 block diagram ............................................................................................................. ................. 38 1.8 outline of functions ...................................................................................................... .............. 39 chapter 2 pin functions .................................................................................................... ........... 41 2.1 pin function list ......................................................................................................... ................. 41 2.2 description of pin functions .............................................................................................. ........ 45 2.2.1 p00 to p06 (port 0) ..................................................................................................... ....................... 45 2.2.2 p10 to p17 (port 1) ..................................................................................................... ....................... 45 2.2.3 p20 to p27 (port 2) ..................................................................................................... ....................... 46 2.2.4 p30 to p33 (port 3) ..................................................................................................... ....................... 46 2.2.5 p40 to p47 (port 4) ..................................................................................................... ....................... 47 2.2.6 p50 to p57 (port 5) ..................................................................................................... ....................... 47 2.2.7 p60 to p67 (port 6) ..................................................................................................... ....................... 47 2.2.8 p70 to p77 (port 7) ..................................................................................................... ....................... 48 2.2.9 p120 (port 12).......................................................................................................... .......................... 48 2.2.10 p130 (port 13)......................................................................................................... ......................... 48 2.2.11 p140 to p145 (port 14) ................................................................................................. ................... 48 2.2.12 av ref .............................................................................................................................. ................ 49 2.2.13 av ss .............................................................................................................................. ................. 49 2.2.14 reset .................................................................................................................. .......................... 49 2.2.15 regc ................................................................................................................... ........................... 49 2.2.16 x1 and x2.............................................................................................................. .......................... 49 2.2.17 xt1 and xt2 ............................................................................................................ ....................... 49 2.2.18 v dd and ev dd ............................................................................................................................... ... 49 2.2.19 v ss and ev ss ............................................................................................................................... .... 49 2.2.20 v pp (flash memory versions only) .................................................................................................. .. 50 2.2.21 ic (mask rom versions only)............................................................................................ .............. 50 2.3 pin i/o circuits and recommended connection of unused pins........................................... 51 chapter 3 cpu architecture ................................................................................................. ..... 55 3.1 memory space.............................................................................................................. ................ 55 3.1.1 internal program memory space........................................................................................... ............. 61 3.1.2 internal data memory space .............................................................................................. ................ 62 3.1.3 special function register (sfr) area.................................................................................... .............. 62 3.1.4 data memory addressing .................................................................................................. ................ 63 3.2 processor registers ....................................................................................................... ............. 68 3.2.1 control registers ....................................................................................................... ......................... 68 3.2.2 general-purpose registers............................................................................................... .................. 71
preliminary user?s manual u15947ej1v1ud 11 3.2.3 special function registers (sfrs) ....................................................................................... .............72 3.3 instruction address addressing ............................................................................................ .....77 3.3.1 relative addressing..................................................................................................... .......................77 3.3.2 immediate addressing .................................................................................................... ....................78 3.3.3 table indirect addressing ............................................................................................... ....................79 3.3.4 register addressing ..................................................................................................... ......................79 3.4 operand address addressing................................................................................................ .....80 3.4.1 implied addressing ...................................................................................................... .......................80 3.4.2 register addressing ..................................................................................................... ......................81 3.4.3 direct addressing ....................................................................................................... ........................82 3.4.4 short direct addressing ................................................................................................. .....................83 3.4.5 special function register (sfr) addressing .............................................................................. ..........84 3.4.6 register indirect addressing............................................................................................ ...................85 3.4.7 based addressing........................................................................................................ .......................86 3.4.8 based indexed addressing ................................................................................................ .................87 3.4.9 stack addressing........................................................................................................ ........................87 chapter 4 port functions ................................................................................................... .........88 4.1 port functions............................................................................................................ ...................88 4.2 port configuration ........................................................................................................ ................90 4.2.1 port 0.................................................................................................................. ................................91 4.2.2 port 1.................................................................................................................. ................................95 4.2.3 port 2.................................................................................................................. ..............................101 4.2.4 port 3.................................................................................................................. ..............................102 4.2.5 port 4.................................................................................................................. ..............................104 4.2.6 port 5.................................................................................................................. ..............................105 4.2.7 port 6.................................................................................................................. ..............................106 4.2.8 port 7.................................................................................................................. ..............................109 4.2.9 port 12................................................................................................................. .............................110 4.2.10 port 13................................................................................................................ ............................111 4.2.11 port 14................................................................................................................ ............................112 4.3 registers controlling port function....................................................................................... ..116 4.4 port function operations .................................................................................................. ........121 4.4.1 writing to i/o port ..................................................................................................... ........................121 4.4.2 reading from i/o port................................................................................................... ....................121 4.4.3 operations on i/o port.................................................................................................. ....................121 chapter 5 external bus interface .......................................................................................122 5.1 external bus interface .................................................................................................... ............122 5.2 registers controlling external bus interface ..........................................................................125 5.3 external bus interface function timing...................................................................................1 27 5.4 example of connection with memory.......................................................................................13 2 chapter 6 clock generator .................................................................................................. ...133 6.1 functions of clock generator .............................................................................................. .....133 6.2 configuration of clock generator.......................................................................................... ...133 6.3 registers controlling clock generator ....................................................................................1 35 6.4 system clock oscillator................................................................................................... ..........141
preliminary user?s manual u15947ej1v1ud 12 6.4.1 x1 oscillator ........................................................................................................... .......................... 141 6.4.2 subsystem clock oscillator .............................................................................................. ................ 141 6.4.3 when subsystem clock is not used........................................................................................ .......... 144 6.4.4 ring-osc oscillator ..................................................................................................... .................... 144 6.4.5 prescaler ............................................................................................................... .......................... 144 6.5 clock generator operation ................................................................................................. ...... 144 6.6 time required to switch between ring-osc clock and x1 input clock............................. 151 6.7 changing system clock and cpu clock settings.................................................................. 152 6.7.1 time required for switching between system clock and cpu clock ................................................. 152 6.8 clock switching flowchart and register setting ................................................................... 153 6.8.1 switching from ring-osc clock to x1 input clock ......................................................................... .. 153 6.8.2 switching from x1 input clock to ring-osc clock ......................................................................... .. 154 6.8.3 switching from x1 input clock to subsystem clock........................................................................ ... 155 6.8.4 switching from subsystem clock to x1 input clock........................................................................ ... 156 6.8.5 register settings....................................................................................................... ....................... 157 chapter 7 16-bit timer/event counters 00 and 01......................................................... 158 7.1 functions of 16-bit timer/event counters 00 and 01 ............................................................ 158 7.2 configuration of 16-bit timer/event counters 00 and 01 ...................................................... 159 7.3 registers controlling 16-bit timer/event counters 00 and 01 ............................................. 163 7.4 operation of 16-bit timer/event counters 00 and 01............................................................. 174 7.4.1 interval timer operation................................................................................................ .................... 174 7.4.2 ppg output operations ................................................................................................... ................. 176 7.4.3 pulse width measurement operations...................................................................................... ........ 178 7.4.4 external event counter operation........................................................................................ ............. 185 7.4.5 square-wave output operation............................................................................................ ............. 187 7.4.6 one-shot pulse output operation ......................................................................................... ............ 188 7.5 cautions for 16-bit timer/event counters 00 and 01............................................................. 193 chapter 8 8-bit timer/event counters 50 and 51........................................................... 197 8.1 functions of 8-bit timer/event counters 50 and 51 .............................................................. 197 8.2 configuration of 8-bit timer/event counters 50 and 51 ........................................................ 199 8.3 registers controlling 8-bit timer/event counters 50 and 51 ............................................... 200 8.4 operations of 8-bit timer/event counters 50 and 51............................................................. 205 8.4.1 operation as interval timer ............................................................................................. ................. 205 8.4.2 operation as external event counter..................................................................................... ........... 207 8.4.3 square-wave output operation............................................................................................ ............. 208 8.4.4 pwm output operation.................................................................................................... ................. 210 8.5 cautions for 8-bit timer/event counters 50 and 51............................................................... 212 chapter 9 8-bit timers h0 and h1........................................................................................ ... 213 9.1 functions of 8-bit timers h0 and h1 ....................................................................................... 213 9.2 configuration of 8-bit timers h0 and h1................................................................................. 21 3 9.3 registers controlling 8-bit timers h0 and h1 ........................................................................ 215 9.4 operation of 8-bit timers h0 and h1 ....................................................................................... 219 9.4.1 operation as interval timer ............................................................................................. ................. 219 9.4.2 operation as pwm pulse generator ........................................................................................ ........ 222 9.4.3 carrier generator mode operation (8-bit timer h1 only) .................................................................. . 228
preliminary user?s manual u15947ej1v1ud 13 chapter 10 watch timer ..................................................................................................... .........235 10.1 functions of watch timer................................................................................................. .......235 10.2 configuration of watch timer ............................................................................................. ....237 10.3 register controlling watch timer......................................................................................... ..237 10.4 watch timer operations ................................................................................................... .......239 10.4.1 watch timer operation .................................................................................................. ..................239 10.4.2 interval timer operation............................................................................................... ....................240 chapter 11 watchdog timer .................................................................................................. ....242 11.1 functions of watchdog timer .............................................................................................. ...242 11.2 configuration of watchdog timer.......................................................................................... .243 11.3 registers controlling watchdog timer ..................................................................................244 11.4 operation of watchdog timer .............................................................................................. ...246 11.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by mask option........246 11.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option ................................................................................................................. ..............247 11.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option)....................................................................................... .248 11.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option)....................................................................................... .251 chapter 12 clock output/buzzer output controller................................................252 12.1 functions of clock output/buzzer output controller...........................................................252 12.2 configuration of clock output/buzzer output controller ....................................................253 12.3 register controlling clock output/buzzer output controller .............................................253 12.4 clock output/buzzer output controller operations .............................................................256 12.4.1 clock output operation ................................................................................................. ..................256 12.4.2 operation as buzzer output ............................................................................................. ...............256 chapter 13 a/d converter ................................................................................................... .......257 13.1 functions of a/d converter ............................................................................................... ......257 13.2 configuration of a/d converter........................................................................................... ....259 13.3 registers controlling a/d converter ...................................................................................... 261 13.4 a/d converter operations................................................................................................. .......265 13.4.1 basic operations of a/d converter ...................................................................................... ............265 13.4.2 input voltage and conversion results ................................................................................... ...........267 13.4.3 a/d converter operation mode ........................................................................................... ............268 13.5 how to read a/d converter characteristics table ...............................................................271 13.6 cautions for a/d converter ............................................................................................... ......273 chapter 14 serial interface uart0 .......................................................................................27 8 14.1 functions of serial interface uart0 ...................................................................................... 278 14.2 configuration of serial interface uart0 ................................................................................27 9 14.3 registers controlling serial interface uart0 .......................................................................282 14.4 operation of serial interface uart0...................................................................................... .286 14.4.1 operation stop mode.................................................................................................... ..................286 14.4.2 asynchronous serial interface (uart) mode .............................................................................. ...287
preliminary user?s manual u15947ej1v1ud 14 14.4.3 dedicated baud rate generator ......................................................................................... ............ 295 chapter 15 serial interface uart6 ...................................................................................... 301 15.1 functions of serial interface uart6...................................................................................... 301 15.2 configuration of serial interface uart6 ............................................................................... 305 15.3 registers controlling serial interface uart6 ...................................................................... 308 15.4 operation of serial interface uart6...................................................................................... 316 15.4.1 operation stop mode .................................................................................................... ................. 316 15.4.2 asynchronous serial interface (uart) mode.............................................................................. ... 317 15.4.3 dedicated baud rate generator .......................................................................................... ............ 335 chapter 16 serial interfaces csi10 and csi11 ................................................................ 344 16.1 functions of serial interfaces csi10 and csi11 ................................................................... 344 16.2 configuration of serial interfaces csi10 and csi11............................................................. 344 16.3 registers controlling serial interfaces csi10 and csi11 .................................................... 347 16.4 operation of serial interfaces csi10 and csi11 ................................................................... 352 16.4.1 operation stop mode .................................................................................................... ................. 352 16.4.2 3-wire serial i/o mode ................................................................................................. .................. 353 chapter 17 serial interface csia0............................................................................................ 3 67 17.1 functions of serial interface csia0 ...................................................................................... . 367 17.2 configuration of serial interface csia0................................................................................. 3 68 17.3 registers controlling serial interface csia0 ........................................................................ 370 17.4 operation of serial interface csia0 ...................................................................................... . 378 17.4.1 operation stop mode .................................................................................................... ................. 378 17.4.2 3-wire serial i/o mode ................................................................................................. .................. 378 17.4.3 3-wire serial i/o mode with automatic transmit/receive function .................................................... 386 chapter 18 multiplier/divider ............................................................................................... .... 413 18.1 functions of multiplier/divider .......................................................................................... ..... 413 18.2 configuration of multiplier/divider...................................................................................... ... 413 18.3 register controlling multiplier/divider .................................................................................. 417 18.4 operations of multiplier/divider ......................................................................................... .... 418 18.4.1 multiplication operation............................................................................................... ................... 418 18.4.2 division operation ..................................................................................................... ..................... 423 chapter 19 interrupt functions............................................................................................. 428 19.1 interrupt function types................................................................................................. ........ 428 19.2 interrupt sources and configuration ..................................................................................... 4 28 19.3 registers controlling interrupt functions ............................................................................ 432 19.4 interrupt servicing operations ........................................................................................... .... 439 19.4.1 maskable interrupt request acknowledgement ............................................................................. . 439 19.4.2 software interrupt request acknowledgement............................................................................. ... 441 19.4.3 multiple interrupt servicing ........................................................................................... .................. 442 19.4.4 interrupt request hold ................................................................................................. ................... 445 chapter 20 key interrupt function........................................................................................ 446 20.1 functions of key interrupt ............................................................................................... ....... 446
preliminary user?s manual u15947ej1v1ud 15 20.2 configuration of key interrupt ........................................................................................... .....446 20.3 register controlling key interrupt....................................................................................... ...447 chapter 21 standby function ................................................................................................ ...448 21.1 standby function and configuration .....................................................................................44 8 21.1.1 standby function....................................................................................................... ......................448 21.1.2 registers controlling standby function................................................................................. ...........450 21.2 standby function operation ............................................................................................... ....452 21.2.1 halt mode .............................................................................................................. ......................452 21.2.2 stop mode .............................................................................................................. .....................456 chapter 22 reset function .................................................................................................. ......459 22.1 register for confirming reset source ...................................................................................46 5 chapter 23 clock monitor ................................................................................................... ......466 23.1 functions of clock monitor ............................................................................................... ......466 23.2 configuration of clock monitor........................................................................................... ....466 23.3 registers controlling clock monitor ...................................................................................... 467 23.4 operation of clock monitor ............................................................................................... ......468 chapter 24 power-on-clear circuit ......................................................................................472 24.1 functions of power-on-clear circuit ...................................................................................... 472 24.2 configuration of power-on-clear circuit................................................................................47 3 24.3 operation of power-on-clear circuit ...................................................................................... 473 24.4 cautions for power-on-clear circuit ...................................................................................... 474 chapter 25 low-voltage detector ........................................................................................476 25.1 functions of low-voltage detector ........................................................................................ 476 25.2 configuration of low-voltage detector..................................................................................47 6 25.3 registers controlling low-voltage detector .........................................................................477 25.4 operation of low-voltage detector ........................................................................................ 480 25.5 cautions for low-voltage detector........................................................................................ .484 chapter 26 regulator ........................................................................................................ ..........488 26.1 outline of regulator ..................................................................................................... ............488 chapter 27 mask options .................................................................................................... ........489 chapter 28 pd78f0148.....................................................................................................................4 90 28.1 internal memory size switching register ..............................................................................491 28.2 internal expansion ram size switching register.................................................................492 28.3 flash memory programming ................................................................................................. ..493 28.3.1 selection of communication mode........................................................................................ ..........493 28.3.2 flash memory programming function ...................................................................................... .......494 28.3.3 connecting flashpro iii ................................................................................................ ..................495 28.3.4 connection on adapter for flash memory writing ......................................................................... ...497
preliminary user?s manual u15947ej1v1ud 16 chapter 29 instruction set................................................................................................. ...... 502 29.1 conventions used in operation list...................................................................................... 5 02 29.1.1 operand identifiers and specification methods .......................................................................... .... 502 29.1.2 description of operation column ........................................................................................ ............ 503 29.1.3 description of flag operation column ................................................................................... .......... 503 29.2 operation list........................................................................................................... ................ 504 29.3 instructions listed by addressing type ............................................................................... 512 chapter 30 electrical specifications (target values) ............................................. 515 chapter 31 package drawings ................................................................................................ 538 chapter 32 cautions for wait.............................................................................................. ... 540 32.1 cautions for wait ........................................................................................................ ............. 540 32.2 peripheral hardware that generates wait ............................................................................ 541 32.3 example of wait occurrence ............................................................................................... ... 542 appendix a development tools............................................................................................... 543 a.1 software package.......................................................................................................... ............ 545 a.2 language processing software.............................................................................................. . 546 a.3 flash memory writing tools ................................................................................................ .... 547 a.4 debugging tools ........................................................................................................... ............ 548 a.4.1 hardware ................................................................................................................ ........................ 548 a.4.2 software................................................................................................................ .......................... 549 appendix b embedded software ............................................................................................. 55 0 appendix c register index .................................................................................................. ....... 551 c.1 register index (in alphabetical order with respect to register names)............................ 551 c.2 register index (in alphabetical order with respect to register symbol) .......................... 555
preliminary user?s manual u15947ej1v1ud 17 list of figures (1/8) figure no. title page 2-1 pin i/o circuit list ........................................................................................................ ............................. 53 3-1 memory map ( pd780143)...................................................................................................................... .56 3-2 memory map ( pd780144)...................................................................................................................... .57 3-3 memory map ( pd780146)...................................................................................................................... .58 3-4 memory map ( pd780148)...................................................................................................................... .59 3-5 memory map ( pd78f0148) .................................................................................................................... 6 0 3-6 data memory addressing ( pd780143) ................................................................................................... 63 3-7 data memory addressing ( pd780144) ................................................................................................... 64 3-8 data memory addressing ( pd780146) ................................................................................................... 65 3-9 data memory addressing ( pd780148) ................................................................................................... 66 3-10 data memory addressing ( pd78f0148) ................................................................................................. 67 3-11 format of program counter .................................................................................................. .................... 68 3-12 format of program status word .............................................................................................. ................. 68 3-13 format of stack pointer .................................................................................................... ........................ 70 3-14 data to be saved to stack memory ........................................................................................... ............... 70 3-15 data to be restored from stack memory ...................................................................................... ........... 70 3-16 configuration of general-purpose registers ................................................................................. ........... 71 4-1 port types .................................................................................................................. .............................. 88 4-2 block diagram of p00, p03, and p05 .......................................................................................... ............. 91 4-3 block diagram of p01 and p06................................................................................................ ................. 92 4-4 block diagram of p02 ........................................................................................................ ....................... 93 4-5 block diagram of p04 ........................................................................................................ ....................... 94 4-6 block diagram of p10 ........................................................................................................ ....................... 95 4-7 block diagram of p11 and p14................................................................................................ ................. 96 4-8 block diagram of p12 ........................................................................................................ ....................... 97 4-9 block diagram of p13 ........................................................................................................ ....................... 98 4-10 block diagram of p15 ....................................................................................................... ........................ 99 4-11 block diagram of p16 and p17............................................................................................... ................ 100 4-12 block diagram of p20 to p27................................................................................................ .................. 101 4-13 block diagram of p30 to p32................................................................................................ .................. 102 4-14 block diagram of p33 ....................................................................................................... ...................... 103 4-15 block diagram of p40 to p47................................................................................................ .................. 104 4-16 block diagram of p50 to p57................................................................................................ .................. 105 4-17 block diagram of p60 to p63................................................................................................ .................. 106 4-18 block diagram of p64, p65, and p67 ......................................................................................... ............ 107 4-19 block diagram of p66 ....................................................................................................... ...................... 108 4-20 block diagram of p70 to p77................................................................................................ .................. 109 4-21 block diagram of p120 ...................................................................................................... ..................... 110 4-22 block diagram of p130 ...................................................................................................... ..................... 111 4-23 block diagram of p140 and p141............................................................................................. .............. 112 4-24 block diagram of p142 ...................................................................................................... ..................... 113 4-25 block diagram of p143 ...................................................................................................... ..................... 114
preliminary user?s manual u15947ej1v1ud 18 list of figures (2/8) figure no. title page 4-26 block diagram of p144 and p145 ............................................................................................. ..............115 4-27 format of port mode register............................................................................................... ..................116 4-28 format of pull-up resistor option register................................................................................. ............119 4-29 format of input switch control register (isc) .............................................................................. ..........120 5-1 memory map when using external bus interface ................................................................................ ..123 5-2 format of memory expansion mode register (mem) .............................................................................1 25 5-3 format of memory expansion wait setting register (mm) .....................................................................12 6 5-4 instruction fetch from external memory ...................................................................................... ...........128 5-5 external memory read timing................................................................................................. ...............129 5-6 external memory write timing................................................................................................ ................130 5-7 external memory read modify write timing.................................................................................... .......131 5-8 connection example of pd780143 and memory ..................................................................................132 6-1 block diagram of clock generator............................................................................................ ..............134 6-2 subsystem clock feedback resistor........................................................................................... ...........135 6-3 format of processor clock control register (pcc) ............................................................................ ....136 6-4 format of ring-osc mode register (rcm)...................................................................................... ......137 6-5 format of main clock mode register (mcm) .................................................................................... ......138 6-6 format of main osc control register (moc)................................................................................... ......139 6-7 format of oscillation stabilization time counter status register (ostc)..............................................139 6-8 format of oscillation stabilization time select register (osts)............................................................1 40 6-9 external circuit of x1 oscillator ........................................................................................... ...................141 6-10 external circuit of subsystem clock oscillator ............................................................................. ..........141 6-11 examples of incorrect resonator connection................................................................................. ........142 6-12 timing diagram of cpu default start using ring-osc ......................................................................... .145 6-13 status transition diagram.................................................................................................. .....................146 6-14 switching from ring-osc clock to x1 input clock ............................................................................ .....153 6-15 switching from x1 input clock to ring-osc clock (flowchart) ..............................................................15 4 6-16 switching from x1 input clock to subsystem clock (flowchart).............................................................15 5 6-17 switching from subsystem clock to x1 input clock (flowchart).............................................................15 6 7-1 block diagram of 16-bit timer/event counter 00 .............................................................................. .....159 7-2 block diagram of 16-bit timer/event counter 01 .............................................................................. .....160 7-3 format of 16-bit timer mode control register 00 (tmc00) ...................................................................16 4 7-4 format of 16-bit timer mode control register 01 (tmc01) ...................................................................16 5 7-5 format of capture/compare control register 00 (crc00) ....................................................................166 7-6 format of capture/compare control register 01 (crc01) ....................................................................167 7-7 format of 16-bit timer output control register 00 (toc00)..................................................................1 68 7-8 format of 16-bit timer output control register 01 (toc01)..................................................................1 69 7-9 format of prescaler mode register 00 (prm00) ................................................................................ ....171 7-10 format of prescaler mode register 01 (prm01) ............................................................................... .....172 7-11 format of port mode register 0 (pm0) ....................................................................................... ............173 7-12 control register settings for interval timer operation..................................................................... .......174
preliminary user?s manual u15947ej1v1ud 19 list of figures (3/8) figure no. title page 7-13 interval timer configuration diagram ....................................................................................... .............. 175 7-14 timing of interval timer operation ......................................................................................... ................ 175 7-15 control register settings for ppg output operation......................................................................... ..... 176 7-16 configuration of ppg output ................................................................................................ .................. 177 7-17 ppg output operation timing ................................................................................................ ................ 177 7-18 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ............... 178 7-19 configuration diagram for pulse width measurement with free-running counter ................................ 179 7-20 timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) ......................................................................... 17 9 7-21 control register settings for measurement of two pulse widths with free-running counter............... 180 7-22 cr01n capture operation with rising edge specified ......................................................................... .. 181 7-23 timing of pulse width measurement operation with free-running counter (with both edges specified).................................................................................................... ................ 181 7-24 control register settings for pulse width measurement with free-running counter and two capture registers .......................................................................................................... ................. 182 7-25 timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified)....................................................................... 18 3 7-26 control register settings for pulse width measurement by means of restart ....................................... 184 7-27 timing of pulse width measurement operation by means of restart (with rising edge specified)....... 184 7-28 control register settings in external event counter mode ................................................................... . 185 7-29 configuration diagram of external event counter ............................................................................ ...... 186 7-30 external event counter operation timing (with rising edge specified)................................................. 186 7-31 control register settings in square-wave output mode....................................................................... . 187 7-32 square-wave output operation timing........................................................................................ .......... 188 7-33 control register settings for one-shot pulse output with software trigger .......................................... 189 7-34 timing of one-shot pulse output operation with software trigger........................................................ 190 7-35 control register settings for one-shot pulse output with external trigger ........................................... 191 7-36 timing of one-shot pulse output operation with external trigger (with rising edge specified) ........... 192 7-37 start timing of 16-bit timer counter 0n (tm0n)............................................................................. ........ 193 7-38 timings after change of compare register during timer count operation .......................................... 193 7-39 capture register data retention timing ..................................................................................... ........... 194 7-40 operation timing of ovf0n flag ............................................................................................. ............... 195 8-1 block diagram of 8-bit timer/event counter 50 ............................................................................... ...... 197 8-2 block diagram of 8-bit timer/event counter 51 ............................................................................... ...... 198 8-3 format of timer clock selection register 50 (tcl50) ......................................................................... .. 200 8-4 format of timer clock selection register 51 (tcl51) ......................................................................... .. 201 8-5 format of 8-bit timer mode control register 50 (tmc50) ..................................................................... 2 02 8-6 format of 8-bit timer mode control register 51 (tmc51) ..................................................................... 2 03 8-7 format of port mode register 1 (pm1) ........................................................................................ ........... 204 8-8 format of port mode register 3 (pm3) ........................................................................................ ........... 204 8-9 interval timer operation timing ............................................................................................. ................ 205 8-10 external event counter operation timing (with rising edge specified)................................................. 207
preliminary user?s manual u15947ej1v1ud 20 list of figures (4/8) figure no. title page 8-11 square-wave output operation timing ........................................................................................ ..........209 8-12 pwm output operation timing ................................................................................................ ...............211 8-13 timing of operation with cr5n changed...................................................................................... ..........212 8-14 8-bit timer counter 5n start timing........................................................................................ ................212 9-1 block diagram of 8-bit timer h0............................................................................................. ................214 9-2 block diagram of 8-bit timer h1............................................................................................. ................214 9-3 format of 8-bit timer h mode register 0 (tmhmd0)............................................................................ .216 9-4 format of 8-bit timer h mode register 1 (tmhmd1)............................................................................ .217 9-5 format of 8-bit timer h carrier control register 1 (tmcyc1) ...............................................................21 8 9-6 register setting in interval timer mode ..................................................................................... .............219 9-7 timing of interval timer operation.......................................................................................... ................220 9-8 register setting in pwm pulse generator mode ................................................................................ ....222 9-9 operation timing in pwm pulse generator mode ................................................................................ ..224 9-10 example of connection between 8-bit timer h1 and 8-bit timer/event counter 51 ..............................228 9-11 transfer timing ............................................................................................................ ...........................229 9-12 register setting in carrier generator mode................................................................................. ...........230 9-13 carrier generator mode operation timing.................................................................................... ..........232 10-1 watch timer block diagram .................................................................................................. .................235 10-2 format of watch timer operation mode register (wtm).......................................................................2 38 10-3 operation timing of watch timer/interval timer ............................................................................. .......241 11-1 block diagram of watchdog timer............................................................................................ ..............244 11-2 format of watchdog timer mode register (wdtm).............................................................................. .245 11-3 format of watchdog timer enable register (wdte) ............................................................................ .246 11-4 operation in stop mode (cpu clock and wdt operation clock: x1 input clock) ...............................248 11-5 operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock).........249 11-6 operation in stop mode (cpu clock: ring-osc clock, wdt operation clock: x1 input clock).........250 11-7 operation in stop mode (cpu clock and wdt operation clock: ring-osc clock) ............................251 11-8 operation in halt mode ..................................................................................................... ...................251 12-1 block diagram of clock output/buzzer output controller..................................................................... ..252 12-2 format of clock output selection register (cks) ............................................................................ ......254 12-3 format of port mode register 14 (pm14) ..................................................................................... ..........255 12-4 remote control output application example.................................................................................. ........256 13-1 block diagram of a/d converter ............................................................................................. ................258 13-2 block diagram of power-fail detection function ............................................................................. .......258 13-3 format of a/d conversion register (adcr)................................................................................... ........259 13-4 format of a/d converter mode register (adm)................................................................................ ......261 13-5 timing chart when boost reference voltage generator is used ..........................................................262 13-6 format of analog input channel specification register (ads) ...............................................................2 63 13-7 format of power-fail comparison mode register (pfm) .......................................................................2 64
preliminary user?s manual u15947ej1v1ud 21 list of figures (5/8) figure no. title page 13-8 format of power-fail comparison threshold register (pft)................................................................. 26 4 13-9 basic operation of a/d converter........................................................................................... ................ 266 13-10 relationship between analog input voltage and a/d conversion result ............................................... 267 13-11 a/d conversion operation .................................................................................................. .................... 268 13-12 power-fail detection (when pfen = 1 and pfcm = 0) ......................................................................... 269 13-13 overall error ............................................................................................................. .............................. 271 13-14 quantization error........................................................................................................ ........................... 271 13-15 zero-scale error .......................................................................................................... ........................... 272 13-16 full-scale error.......................................................................................................... ............................. 272 13-17 integral linearity error .................................................................................................. .......................... 272 13-18 differential linearity error .............................................................................................. ......................... 272 13-19 example of method of reducing current consumption in standby mode .............................................. 273 13-20 storing conversion result in adcr and timing of data read from adcr ........................................... 274 13-21 analog input pin connection ............................................................................................... ................... 275 13-22 timing of a/d conversion end interrupt request generation ................................................................ 2 76 13-23 timing of a/d converter sampling and a/d conversion start delay...................................................... 277 14-1 block diagram of serial interface uart0.................................................................................... ........... 280 14-2 format of asynchronous serial interface operation mode register 0 (asim0)...................................... 282 14-3 format of asynchronous serial interface reception error status register 0 (asis0)............................ 284 14-4 format of baud rate generator control register 0 (brgc0) ................................................................ 285 14-5 format of normal uart transmit/receive data................................................................................ .... 290 14-6 example of normal uart transmit/receive data format ..................................................................... 290 14-7 normal transmission completion interrupt request timing................................................................... 2 92 14-8 reception completion interrupt request timing .............................................................................. ...... 293 14-9 noise filter circuit ....................................................................................................... ........................... 294 14-10 configuration of baud rate generator...................................................................................... .............. 295 14-11 permissible baud rate range during reception .............................................................................. ..... 299 15-1 lin transmission operation ................................................................................................. .................. 302 15-2 lin reception operation .................................................................................................... .................... 303 15-3 port configuration for lin reception operation ............................................................................. ........ 304 15-4 block diagram of serial interface uart6.................................................................................... ........... 306 15-5 format of asynchronous serial interface operation mode register 6 (asim6)...................................... 308 15-6 format of asynchronous serial interface reception error status register 6 (asis6)............................ 310 15-7 format of asynchronous serial interface transmission status register 6 (asif6)................................ 311 15-8 format of clock selection register 6 (cksr6) ............................................................................... ....... 312 15-9 format of baud rate generator control register 6 (brgc6) ................................................................ 313 15-10 format of asynchronous serial interface control register 6 (asicl6) .................................................. 314 15-11 format of normal uart transmit/receive data............................................................................... ..... 323 15-12 example of normal uart transmit/receive data format ..................................................................... 32 4 15-13 normal transmission completion interrupt request timing................................................................... 326 15-14 processing flow of continuous transmission ................................................................................ ........ 328 15-15 timing of starting continuous transmission ................................................................................ .......... 329
preliminary user?s manual u15947ej1v1ud 22 list of figures (6/8) figure no. title page 15-16 timing of ending continuous transmission.................................................................................. ..........330 15-17 reception completion interrupt request timing ............................................................................. .......331 15-18 reception error interrupt................................................................................................. ........................332 15-19 noise filter circuit...................................................................................................... .............................333 15-20 sbf transmission.......................................................................................................... .........................333 15-21 sbf reception ............................................................................................................. ...........................334 15-22 configuration of baud rate generator...................................................................................... ..............336 15-23 permissible baud rate range during reception .............................................................................. .....341 15-24 transfer rate during continuous transmission .............................................................................. .......343 16-1 block diagram of serial interface csi10.................................................................................... .............345 16-2 block diagram of serial interface csi11 ( pd780146, 780148, and 78f0148 only) .............................345 16-3 format of serial operation mode register 10 (csim10) ....................................................................... .348 16-4 format of serial operation mode register 11 (csim11) ....................................................................... .349 16-5 format of serial clock selection register 10 (csic10)...................................................................... ....350 16-6 format of serial clock selection register 11 (csic11)...................................................................... ....351 16-7 timing in 3-wire serial i/o mode ........................................................................................... .................361 16-8 timing of clock/data phase................................................................................................. ...................363 16-9 output operation of first bit .............................................................................................. .....................364 16-10 output value of so1n pin (last bit)....................................................................................... .................365 17-1 block diagram of serial interface csia0 .................................................................................... ............369 17-2 format of automatic data transfer address count register 0 (adtc0) ................................................370 17-3 format of serial operation mode specification register 0 (csima0).....................................................371 17-4 format of serial status register 0 (csis0) ................................................................................. ...........372 17-5 format of serial trigger register 0 (csit0) ................................................................................ ...........374 17-6 format of divisor selection register 0 (brgca0)............................................................................ ......375 17-7 format of automatic data transfer address point specification register 0 (adtp0) ............................375 17-8 format of automatic data transfer interval specification register 0 (adti0) ........................................377 17-9 3-wire serial i/o mode timing.............................................................................................. ..................383 17-10 format of transmit/receive data ........................................................................................... ................384 17-11 transfer bit order switching circuit ...................................................................................... ..................385 17-12 automatic transmission/reception mode operation timings.................................................................39 4 17-13 automatic transmission/reception mode flowchart ........................................................................... ...395 17-14 internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode)..................................................................................... ....396 17-15 automatic transmission mode operation timing .............................................................................. .....398 17-16 automatic transmission mode flowchart ..................................................................................... ..........399 17-17 internal buffer ram operation in 6-byte transmission (in automatic transmission mode) ...................400 17-18 repeat transmission mode operation timing................................................................................. .......402 17-19 repeat transmission mode flowchart........................................................................................ ............403 17-20 internal buffer ram operation in 6-byte transmission (in repeat transmission mode)........................404 17-21 format of csia0 transmit/receive data ..................................................................................... ...........406 17-22 automatic transmission/reception suspension and restart..................................................................4 07
preliminary user?s manual u15947ej1v1ud 23 list of figures (7/8) figure no. title page 17-23 system configuration when busy control option is used ..................................................................... 408 17-24 operation timing when busy control option is used (when busylv0 = 1) ........................................ 409 17-25 busy signal and wait release (when busylv0 = 1)........................................................................... . 409 17-26 operation timing when busy & strobe control options are used (when busylv0 = 1)..................... 410 17-27 operation timing of bit shift detection function by busy signal (when busylv0 = 0)........................ 411 17-28 automatic data transmit/receive interval time............................................................................. ........ 412 18-1 block diagram of multiplier/divider ........................................................................................ ................. 414 18-2 format of remainder data register 0 (sdr0) ................................................................................. ...... 415 18-3 format of multiplication/division data register a0 (mda0h, mda0l) ................................................... 416 18-4 format of multiplication/division data register b0 (mdb0).................................................................. .. 416 18-5 format of multiplier/divider control register 0 (dmuc0) .................................................................... ... 417 18-6 timing chart of multiplication operation (00dah 0093h).................................................................... 419 18-7 timing chart when multiplication is executed successively (00dah 0093h ffffh ffffh)..... 421 18-8 example of multiplication operation by multiplier/divider (4 bits 4 bits (0111b 0101b)) .................. 422 18-9 timing chart of division operation (dcba2586h 0018h)................................................................... 424 18-10 timing chart when division is executed successively (dcba2586 0018h ffffffffh ffffh) .................................................................................... 426 18-11 example of division operation by multiplier/divider (4 bits 2 bits (1001b 10b)) .............................. 427 19-1 basic configuration of interrupt function.................................................................................. .............. 431 19-2 format of interrupt request flag registers (if0l, if0h, if1l, if1h)..................................................... 434 19-3 format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h)................................................. 435 19-4 format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h)......................................... 436 19-5 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ................................................................... 437 19-6 format of program status word .............................................................................................. ............... 438 19-7 interrupt request acknowledgement processing algorithm ................................................................... 44 0 19-8 interrupt request acknowledgement timing (minimum time) ............................................................... 441 19-9 interrupt request acknowledgement timing (maximum time) .............................................................. 441 19-10 examples of multiple interrupt servicing.................................................................................. ............... 443 19-11 interrupt request hold.................................................................................................... ........................ 445 20-1 block diagram of key interrupt ............................................................................................. .................. 446 20-2 format of key return mode register (krm) ................................................................................... ....... 447 21-1 operation timing when stop mode is released ................................................................................ . 449 21-2 format of oscillation stabilization time counter status register (ostc) ............................................. 450 21-3 format of oscillation stabilization time select register (osts) ........................................................... 4 51 21-4 halt mode release by interrupt request generation.......................................................................... . 454 21-5 halt mode release by reset input ........................................................................................... ......... 455 21-6 stop mode release by interrupt request generation .......................................................................... 457 21-7 stop mode release by reset input ........................................................................................... ........ 458
preliminary user?s manual u15947ej1v1ud 24 list of figures (8/8) figure no. title page 22-1 block diagram of reset function............................................................................................ ................460 22-2 timing of reset by reset input ............................................................................................. ...............461 22-3 timing of reset due to watchdog timer overflow ............................................................................. ....461 22-4 timing of reset in stop mode by reset input................................................................................ ....461 22-5 format of reset control flag register (resf)............................................................................... ........465 23-1 block diagram of clock monitor ............................................................................................. .................466 23-2 format of clock monitor mode register (clm)................................................................................ .......467 23-3 timing of clock monitor .................................................................................................... ......................469 24-1 block diagram of power-on-clear circuit.................................................................................... ............473 24-2 timing of internal reset signal generation in power-on-clear circuit....................................................473 24-3 example of software processing after release of reset ...................................................................... .474 25-1 block diagram of low-voltage detector ...................................................................................... ...........476 25-2 format of low-voltage detection register (lvim)............................................................................ ......478 25-3 format of low-voltage detection level selection register (lvis) .........................................................479 25-4 timing of low-voltage detector internal reset signal generation .........................................................481 25-5 timing of low-voltage detector interrupt signal generation ................................................................. .483 25-6 example of software processing after release of reset ...................................................................... .485 25-7 example of software processing of lvi interrupt............................................................................ ........487 26-1 block diagram of regulator periphery ....................................................................................... .............488 28-1 format of internal memory size switching register (ims).................................................................... ..491 28-2 format of internal expansion ram size switching register (ixs) .........................................................492 28-3 communication mode selection format ........................................................................................ .........494 28-4 connection of flashpro iii in 3-wire serial i/o mode ....................................................................... .......495 28-5 connection of flashpro iii in 3-wire serial i/o mode (using handshake) ..............................................495 28-6 connection of flashpro iii in uart (uart0) mode............................................................................ ....496 28-7 connection of flashpro iii in uart (uart0) mode (using handshake) ................................................496 28-8 connection of flashpro iii in uart (uart6) mode............................................................................ ....496 28-9 example of wiring adapter for flash memory writing in 3-wire serial i/o mode ...................................497 28-10 example of wiring adapter for flash memory writing in 3-wire serial i/o mode (using handshake) ....498 28-11 example of wiring adapter for flash memory writing in uart (uart0) mode .....................................499 28-12 example of wiring adapter for flash memory writing in uart (uart0) mode (using handshake) .....500 28-13 example of wiring adapter for flash memory writing in uart (uart6) mode .....................................501 a-1 development tool configuration.............................................................................................. ...............544
preliminary user?s manual u15947ej1v1ud 25 list of tables (1/3) table no. title page 1-1 flash memory versions corresponding to mask options of mask rom versions ................................... 31 2-1 pin i/o circuit types ....................................................................................................... .......................... 51 3-1 set values of internal memory size switching register (ims) and internal expansion ram size switching register (ixs)..................................................................... 55 3-2 internal memory capacity .................................................................................................... ..................... 61 3-3 vector table ................................................................................................................ ............................. 61 3-4 internal expansion ram capacity ............................................................................................. ............... 62 3-5 special function register list .............................................................................................. .................... 73 4-1 port functions.............................................................................................................. ............................. 89 4-2 port configuration .......................................................................................................... ........................... 90 4-3 pull-up resistor of port 6 .................................................................................................. ...................... 106 4-4 settings of port mode register and output latch when using alternate function ................................ 117 5-1 pin functions in external memory expansion mode............................................................................. .. 122 5-2 state of ports 4 to 6 pins in external memory expansion mode............................................................. 122 6-1 configuration of clock generator ............................................................................................ ............... 133 6-2 relationship between cpu clock and minimum instruction execution time ......................................... 137 6-3 relationship between operation clocks in each operation status ........................................................ 150 6-4 oscillation control flags and clock oscillation status...................................................................... ...... 150 6-5 time required to switch between ring-osc clock and x1 input clock................................................ 151 6-6 maximum time required for cpu clock switchover.............................................................................. 152 6-7 clock and register setting .................................................................................................. ................... 157 7-1 configuration of 16-bit timer/event counters 00 and 01...................................................................... .. 159 7-2 ti00n pin valid edge and cr00n, cr01n capture trigger .................................................................... 161 7-3 ti01n pin valid edge and cr00n capture trigger .............................................................................. ... 161 8-1 configuration of 8-bit timer/event counters 50 and 51....................................................................... ... 199 9-1 configuration of 8-bit timers h0 and h1 ..................................................................................... ........... 213 10-1 watch timer interrupt time ................................................................................................. ................... 236 10-2 interval timer interval time ............................................................................................... ..................... 236 10-3 watch timer configuration .................................................................................................. ................... 237 10-4 watch timer interrupt time ................................................................................................. ................... 239 10-5 interval timer interval time ............................................................................................... ..................... 240 11-1 loop detection time of watchdog timer...................................................................................... .......... 242 11-2 mask option setting and watchdog timer operation mode................................................................... 243 11-3 configuration of watchdog timer ............................................................................................ ............... 243
preliminary user?s manual u15947ej1v1ud 26 list of tables (2/3) table no. title page 12-1 clock output/buzzer output controller configuration........................................................................ .....253 13-1 configuration of a/d converter ............................................................................................. ..................259 13-2 settings of adcs and adce .................................................................................................. ................262 13-3 a/d converter sampling time and a/d conversion start delay time (adm set value) ........................277 14-1 configuration of serial interface uart0 .................................................................................... .............279 14-2 cause of reception error................................................................................................... .....................294 14-3 set data of baud rate generator ............................................................................................ ...............298 14-4 maximum/minimum permissible baud rate error................................................................................ ...300 15-1 configuration of serial interface uart6 .................................................................................... .............305 15-2 write processing and writing to txb6 during execution of continuous transmission...........................327 15-3 cause of reception error................................................................................................... .....................332 15-4 set data of baud rate generator ............................................................................................ ...............340 15-5 maximum/minimum permissible baud rate error................................................................................ ...342 16-1 configuration of serial interfaces csi10 and csi11 ......................................................................... ......344 16-2 so1n pin status ............................................................................................................ .........................366 17-1 configuration of serial interface csia0 .................................................................................... ..............368 17-2 relationship between buffer ram address values and adtp0 setting values ....................................376 18-1 configuration of multiplier/divider ........................................................................................ ...................413 18-2 functions of mda0 during operation execution............................................................................... ......415 19-1 interrupt source list...................................................................................................... ..........................429 19-2 flags corresponding to interrupt request sources ........................................................................... .....433 19-3 ports corresponding to egpn and egnn ....................................................................................... ........437 19-4 time from generation of maskable interrupt request until servicing.....................................................439 19-5 interrupt request enabled for multiple interrupt servicing during interrupt servicing ............................442 20-1 assignment of key interrupt detection pins................................................................................. ...........446 20-2 configuration of key interrupt ............................................................................................. ....................446 21-1 relationship between halt mode, stop mode, and clock..................................................................448 21-2 operating statuses in halt mode............................................................................................ ..............452 21-3 operation after halt mode release.......................................................................................... ............455 21-4 operating statuses in stop mode ............................................................................................ .............456 21-5 operation after stop mode release .......................................................................................... ...........458 22-1 hardware statuses after reset.............................................................................................. .................462 22-2 resf status when reset request is generated................................................................................ ...465 23-1 configuration of clock monitor............................................................................................. ...................466
preliminary user?s manual u15947ej1v1ud 27 list of tables (3/3) table no. title page 23-2 operation status of clock monitor (when clme = 1) .......................................................................... .. 468 27-1 flash memory versions supporting mask options of mask rom versions ........................................... 489 28-1 differences between pd78f0148 and mask rom versions ................................................................ 490 28-2 internal memory size switching register settings ........................................................................... ...... 491 28-3 internal expansion ram size switching register settings.................................................................... . 492 28-4 communication mode list .................................................................................................... .................. 493 28-5 main functions of flash memory programming ................................................................................. .... 494 29-1 operand identifiers and specification methods .............................................................................. ........ 502 32-1 registers that generate wait and number of cpu wait clocks ........................................................... 541 32-2 number of wait clocks and number of execution clocks on occurrence of wait (a/d converter)........ 542
preliminary user?s manual u15947ej1v1ud 28 chapter 1 outline 1.1 features { rom, ram capacities data memory item part number program memory (rom) internal high-speed ram internal expansion ram pd780143 24 kb pd780144 32 kb ? pd780146 48 kb pd780148 mask rom 60 kb 1024 bytes pd78f0148 flash memory 60 kb note 1024 bytes 1024 bytes note note the internal flash memory and internal expansion ram capacities can be changed using the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). { buffer ram: 32 bytes { external memory expansion space: 64 kb { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { short startup is possible via the cpu default start using the on-chip ring-osc { on-chip clock monitor function using on-chip ring-osc { on-chip watchdog timer (operable with ring-osc clock) { on-chip uart supporting lin (local interconnect network) bus { on-chip multiplier/divider { on-chip key interrupt function { on-chip external bus interface function { on-chip clock output/buzzer output controller { on-chip regulator { minimum instruction execution time can be changed from high speed (0.2 s: @ 10 mhz operation with x1 input clock) to ultra low-speed (122 s: @ 32.768 khz operation with subsystem clock) { i/o ports: 67 (n-ch open drain: 4) { timer pd780143, 780144: 7 channels pd780146, 780148, 78f0148: 8 channels { serial interface pd780143, 780144: 3 channels (uart: 1 channel, csi/uart note : 1 channel, csi with automatic transmit/receive function: 1 channel) pd780146, 780148, 78f0148: 4 channels (uart: 1 channel, csi: 1 channel, csi/uart note : 1 channel, csi with automatic transmit/receive function: 1 channel) { 10-bit resolution a/d converter: 8 channels { supply voltage: v dd = 2.7 to 5.5 v note select either of the functions of these alternate-function pins.
chapter 1 outline preliminary user?s manual u15947ej1v1ud 29 1.2 applications { automotive equipment ? system control for body electricals (power windows, keyless entry reception, etc.) ? sub-microcontrollers for control { home audio, car audio { av equipment { pc peripheral equipment (keyboards, etc.) { household electrical appliances ? outdoor air conditioner units ? microwave ovens, electric rice cookers { industrial equipment ? pumps ? vending machines ? fa 1.3 ordering information (1) mask rom version part number package pd780143gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780143gc- -8bt 80-pin plastic qfp (14 14) pd780144gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780144gc- -8bt 80-pin plastic qfp (14 14) pd780146gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780146gc- -8bt 80-pin plastic qfp (14 14) pd780148gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780148gc- -8bt 80-pin plastic qfp (14 14) pd780143gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780143gc(a)- -8bt 80-pin plastic qfp (14 14) pd780144gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780144gc(a)- -8bt 80-pin plastic qfp (14 14) pd780146gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780146gc(a)- -8bt 80-pin plastic qfp (14 14) pd780148gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780148gc(a)- -8bt 80-pin plastic qfp (14 14) pd780143gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780143gc(a1)- -8bt 80-pin plastic qfp (14 14) pd780144gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780144gc(a1)- -8bt 80-pin plastic qfp (14 14) pd780146gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780146gc(a1)- -8bt 80-pin plastic qfp (14 14) pd780148gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780148gc(a1)- -8bt 80-pin plastic qfp (14 14) remark indicates rom code suffix.
chapter 1 outline preliminary user?s manual u15947ej1v1ud 30 (2) flash memory part number package pd78f0148m1gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m1gc-8bt 80-pin plastic qfp (14 14) pd78f0148m2gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m2gc-8bt 80-pin plastic qfp (14 14) pd78f0148m3gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m3gc-8bt 80-pin plastic qfp (14 14) pd78f0148m4gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m4gc-8bt 80-pin plastic qfp (14 14) pd78f0148m5gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m5gc-8bt 80-pin plastic qfp (14 14) pd78f0148m6gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m6gc-8bt 80-pin plastic qfp (14 14) pd78f0148m1gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m1gc(a)-8bt 80-pin plastic qfp (14 14) pd78f0148m2gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m2gc(a)-8bt 80-pin plastic qfp (14 14) pd78f0148m3gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m3gc(a)-8bt 80-pin plastic qfp (14 14) pd78f0148m4gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m4gc(a)-8bt 80-pin plastic qfp (14 14) pd78f0148m5gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m5gc(a)-8bt 80-pin plastic qfp (14 14) pd78f0148m6gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd78f0148m6gc(a)-8bt 80-pin plastic qfp (14 14)
chapter 1 outline preliminary user?s manual u15947ej1v1ud 31 mask rom versions ( pd780143, 780144, 780146, and 780148) include mask options. when ordering, it is possible to select ?power-on-clear (poc) circuit can be used/cannot be used?, ?ring-osc clock can be stopped/cannot be stopped by software? and ?pull-up resistor incorporated/not incorporated in 1-bit units (p60 to p63)?. flash memory versions corresponding to the mask options of the mask rom versions are as follows. table 1-1. flash memory versions corresponding to mask options of mask rom versions mask option poc circuit ring-osc flash memory versions (part number) cannot be stopped pd78f0148m1gk-9eu pd78f0148m1gc-8bt pd78f0148m1gk(a)-9eu pd78f0148m1gc(a)-8bt poc cannot be used can be stopped by software pd78f0148m2gk-9eu pd78f0148m2gc-8bt pd78f0148m2gk(a)-9eu pd78f0148m2gc(a)-8bt cannot be stopped pd78f0148m3gk-9eu pd78f0148m3gc-8bt pd78f0148m3gk(a)-9eu pd78f0148m3gc(a)-8bt poc used (v poc = 2.85 v 0.15 v) can be stopped by software pd78f0148m4gk-9eu pd78f0148m4gc-8bt pd78f0148m4gk(a)-9eu pd78f0148m4gc(a)-8bt cannot be stopped pd78f0148m5gk-9eu pd78f0148m5gc-8bt pd78f0148m5gk(a)-9eu pd78f0148m5gc(a)-8bt poc used (v poc = 3.5 v 0.2 v) can be stopped by software pd78f0148m6gk-9eu pd78f0148m6gc-8bt pd78f0148m6gk(a)-9eu pd78f0148m6gc(a)-8bt
chapter 1 outline preliminary user?s manual u15947ej1v1ud 32 1.4 quality grade (1) mask rom version part number package quality grade pd780143gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd780143gc- -8bt 80-pin plastic qfp (14 14) standard pd780144gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd780144gc- -8bt 80-pin plastic qfp (14 14) standard pd780146gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd780146gc- -8bt 80-pin plastic qfp (14 14) standard pd780148gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd780148gc- -8bt 80-pin plastic qfp (14 14) standard pd780143gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780143gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780144gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780144gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780146gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780146gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780148gk(a)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780148gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780143gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780143gc(a1)- -8bt 80-pin plastic qfp (14 14) special pd780144gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780144gc(a1)- -8bt 80-pin plastic qfp (14 14) special pd780146gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780146gc(a1)- -8bt 80-pin plastic qfp (14 14) special pd780148gk(a1)- -9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd780148gc(a1)- -8bt 80-pin plastic qfp (14 14) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 33 (2) flash memory version part number package quality grade pd78f0148m1gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m1gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m2gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m2gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m3gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m3gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m4gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m4gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m5gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m5gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m6gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) standard pd78f0148m6gc-8bt 80-pin plastic qfp (14 14) standard pd78f0148m1gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m1gc(a)-8bt 80-pin plastic qfp (14 14) special pd78f0148m2gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m2gc(a)-8bt 80-pin plastic qfp (14 14) special pd78f0148m3gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m3gc(a)-8bt 80-pin plastic qfp (14 14) special pd78f0148m4gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m4gc(a)-8bt 80-pin plastic qfp (14 14) special pd78f0148m5gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m5gc(a)-8bt 80-pin plastic qfp (14 14) special pd78f0148m6gk(a)-9eu 80-pin plastic tqfp (fine pitch) (12 12) special pd78f0148m6gc(a)-8bt 80-pin plastic qfp (14 14) special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 34 1.5 pin configuration (top view) ? 80-pin plastic tqfp (fine pitch) (12 12) pd780143gk- -9eu, 780144gk- -9eu, 780146gk- -9eu, 780148gk- -9eu, pd780143gk(a)- -9eu, 780144gk(a)- -9eu, 780146gk(a)- -9eu, pd780148gk(a)- -9eu, 780143gk(a1)- -9eu, 780144gk(a1)- -9eu, pd780146gk(a1)- -9eu, 780148gk(a1)- -9eu, pd78f0148m1gk-9eu, 78f0148m2gk-9eu, 78f0148m3gk-9eu, 78f0148m4gk-9eu, pd78f0148m5gk-9eu, 78f0148m6gk-9eu, 78f0148m1gk(a)-9eu, 78f0148m2gk(a)-9eu, pd78f0148m3gk(a)-9eu, 78f0148m4gk(a)-9eu, 78f0148m5gk(a)-9eu, 78f0148m6gk(a)-9eu ? 80-pin plastic qfp (14 14) pd780143gc- -8bt, 780144gc- -8bt, 780146gc- -8bt, 780148gc- -8bt, pd780143gc(a)- -8bt, 780144gc(a)- -8bt, 780146gc(a)- -8bt, pd780148gc(a)- -8bt, 780143gc(a1)- -8bt, 780144gc(a1)- -8bt, pd780146gc(a1)- -8bt, 780148gc(a1)- -8bt, pd78f0148m1gc-8bt, 78f0148m2gc-8bt, 78f0148m3gc-8bt, 78f0148m4gc-8bt, pd78f0148m5gc-8bt, 78f0148m6gc-8bt, 78f0148m1gc(a)-8bt, 78f0148m2gc(a)-8bt, pd78f0148m3gc(a)-8bt, 78f0148m4gc(a)-8bt, 78f0148m5gc(a)-8bt, 78f0148m6gc(a)-8bt
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 av ref av ss p120/intp0 p33/ti51/to50/intp4 p32/intp3 p31/intp2 p30/intp1 ic (v pp ) v dd regc v ss x1 x2 reset xt1 xt2 p130 p10/sck10/txd0 p11/si10/rxd0 p12/so10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 p64/rd p65/wr p66/wait p67/astb p00/ti000 p01/ti010/to00 p02/so11 note p03/si11 note p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p70/kr0 p71/kr1 p72/kr2 p73/kr3 p74/kr4 p75/kr5 p76/kr6 p77/kr7 p40/ad0 p41/ad1 p42/ad2 p43/ad3 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p140/pcl/intp6 p141/buz/busy0/intp7 p63 p62 ev ss ev dd p61 p60 p142/scka0 p143/sia0 p144/soa0 p145/stb0 p06/ti011 note /to01 note p05/ssi11 note /ti001 note p04/sck11 note note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148. cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av ref pin to v dd . 3. connect the av ss pin to v ss . 4. when using the regulator, connect the regc pin to v ss via 0.1 f capacitor. when the regulator is not used, connect the regc pin directly to v dd . remark figures in parentheses apply only to the pd78f0148.
chapter 1 outline preliminary user?s manual u15947ej1v1ud 36 pin identification a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input astb: address strobe av ref : analog reference voltage av ss : analog ground busy0: serial busy input buz: buzzer output ev dd : power supply for port ev ss : ground for port ic: internally connected intp0 to intp7: external interrupt input kr0 to kr7: key return p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p120: port 12 p130: port 13 p140 to p145: port 14 pcl: programmable clock output regc: regulator capacitance reset: reset rxd0, rxd6: receive data rd: read strobe sck10, sck11 note , scka0: serial clock input/output si10, si11 note , sia0: serial data input so10, so11 note , soa1: serial data output ssi11 note : serial interface chip select input stb0: serial strobe ti000, ti010, ti001 note , ti011 note , ti50, ti51: timer input to00, to01 note , to50, to51, toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v pp : programming power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (x1 input clock) xt1, xt2: crystal (subsystem clock) note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148.
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 37 1.6 78k0/kxx series lineup the lineup of products in the 78k0/kxx series (under development or in planning) is shown below. pd78f0103 flash memory: 24 kb, ram: 768 bytes mask rom: 24 kb, ram: 768 bytes mask rom: 16 kb, ram: 768 bytes mask rom: 8 kb, ram: 512 bytes pd780103 pd780102 pd780101 78k0/kb1 series: 30-pin (7.62 mm 0.65 mm pitch) pd78f0114 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780114 pd780113 pd780112 mask rom: 8 kb, ram: 512 bytes pd780111 78k0/kc1 series: 44-pin (10 10 mm 0.8 mm pitch) pd78f0124 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780124 pd780123 pd780122 mask rom: 8 kb, ram: 512 bytes pd780121 78k0/kd1 series: 52-pin (10 10 mm 0.65 mm pitch) pd78f0148 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram: 2 kb mask rom: 32 kb, ram: 1 kb pd780148 pd780146 pd780144 mask rom: 24 kb, ram: 1 kb pd780143 78k0/kf1 series: 80-pin (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) pd78f0134 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780134 pd780133 pd780132 mask rom: 8 kb, ram: 512 bytes pd780131 pd78f0138 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram : 2 kb pd780138 pd780136 78k0/ke1 series: 64-pin (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch, 14 14 mm 0.8 mm pitch)
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 38 1.7 block diagram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 78k/0 cpu core internal high-speed ram rom (flash memory) v ss , ev ss ic (v pp ) v dd , ev dd serial interface csi10 si10/p11 so10/p12 sck10/p10 ani0/p20 to ani7/p27 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 8 a/d converter rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 8 system control reset x1 x2 clock monitor power on clear/ low voltage indicator reset control external access port 6 p60 to p67 8 port 7 p70 to p77 port 12 p120 port 13 p130 8 p40 to p47 8 p50 to p57 8 port 14 p140 to p145 6 ring-osc ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 xt1 xt2 16-bit timer/ note event counter 01 to01 note /ti011 note /p06 ti001 note /p05 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi11 note si11 note /p03 so11 note /p02 sck11 note /p04 ssi11 note /p05 serial interface csia0 sia0/p143 soa0/p144 scka0/p142 stb0/p145 busy0/p141 intp5/p16 intp6/p140, intp7/p141 2 buzzer output buz/p141 clock output control pcl/p140 key return 8 8 8 kr0/p70 to kr7/p77 multiplier & divider voltage regulator regc note pd780146, 780148, and 78f0148 only. remark items in parentheses are available only in the pd78f0148.
chapter 1 outline preliminary user ? s manual u15947ej1v1ud 39 1.8 outline of functions (1/2) item pd780143 pd780144 pd780146 pd780148 pd78f0148 rom 24 kb 32 kb 48 kb 60 kb 60 kb note (flash memory) high-speed ram 1 kb expansion ram ? 1 kb 1 kb note internal memory buffer ram 32 bytes memory space 64 kb x1 input clock (oscillation frequency) ceramic/crystal/external clock oscillation regc pin is directly connected to v dd 10 mhz: v dd = 4.0 to 5.5 v, 8.38 mhz: v dd = 3.3 to 5.5 v, 5 mhz: v dd = 2.7 to 5.5 v 0.1 f capacitor is connected to regc pin 8.38 mhz: v dd = 3.3 to 5.5 v, 5 mhz: v dd = 2.7 to 5.5 v ring-osc clock (oscillation frequency) on-chip ring oscillation (240 khz (typ.)) subsystem clock (oscillation frequency) crystal/external clock oscillation (32.768 khz) general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (x1 input clock: @ f xp = 10 mhz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (typ.) (ring-osc clock: @ f r = 240 khz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: @ f xt = 32.768 khz operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits 4 banks) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 67 cmos i/o 54 cmos input 8 cmos output 1 n-ch open-drain output 4 timers 16-bit timer/event counter: 2 channels (1 channel only in the pd780143, 780144) 8-bit timer/event counter: 2 channels 8-bit timer: 2 channels watch timer 1 channel watchdog timer: 1 channel timer outputs 5 (pwm output: 3) 6 (pwm output: 3) clock output 78.125 khz, 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (x1 input clock: 10 mhz) 32.768 khz (subsystem clock: 32.768 khz) buzzer output 1.22 khz, 2.44 khz, 4.88 khz, 9.77 khz (x1 input clock: 10 mhz) a/d converter 10-bit resolution 8 channels note the internal flash memory capacity and internal expansion ram capacity can be changed using the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs).
chapter 1 outline preliminary user?s manual u15947ej1v1ud 40 (2/2) item pd780143 pd780144 pd780146 pd780148 pd78f0148 serial interface uart mode supporting lin-bus: 1 channel 3-wire serial i/o mode: 1 channel (no channel in the pd780143, 780144) 3-wire serial i/o mode with automatic transmit/receive function: 1 channel 3-wire serial i/o mode/uart mode note : 1 channel multiplier/divider 16 bits 16 bits = 32 bits (multiplication) 32 bits 16 bits = 32 bits remainder of 16 bits (division) internal 17 20 vectored interrupt sources external 9 key interrupt key interrupt (intkr) occurs by detecting falling edge of key input pins (kr0 to kr7). reset reset using reset pin internal reset by watchdog timer internal reset by clock monitor internal reset by power-on-reset internal reset by low-voltage detector supply voltage v dd = 2.7 to 5.5 v operating ambient temperature standard products, (a) products: t a = ? 40 to +85 c (a1) products: t a = ? 40 to +110 c ( pd780143, 780144, 780146, and 780148 only) package 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) note select either of the functions of these alternate-function pins. an outline of the timer is shown below. 16-bit timer/ event counters 00 and 01 note 1 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 watch timer watchdog timer interval timer 2 channels 2 channels 2 channels 1 channel note 2 1 channel operation mode external event counter 2 channels 2 channels ??? timer output 2 outputs 2 outputs 2 outputs ?? ppg output 2 outputs ???? pwm output ? 2 outputs 2 outputs ?? pulse width measurement 4 inputs ???? square-wave output 2 outputs 2 outputs ??? function interrupt source 4221 ? notes 1. 16-bit timer/event counter 01 is available only in the pd780146, 780148, and 78f0148. 2. in the watch timer, the watch timer function and interval timer function can be used simultaneously.
preliminary user?s manual u15947ej1v1ud 41 chapter 2 pin functions 2.1 pin function list (1) port pins (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ad0 to ad7 p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input a8 to a15 note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 42 (1) port pins (2/2) pin name i/o function after reset alternate function p60 to p63 n-ch open-drain i/o port. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. ? p64 rd p65 wr p66 wait p67 i/o port 6. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input astb p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input kr0 to kr7 p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? p140 pcl/intp6 p141 buz/busy0/ intp7 p142 scka0 p143 sia0 p144 soa0 p145 i/o port 14. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input stb0
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 43 (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 p120 intp1 to intp3 p30 to p32 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p141/buz/busy0 si10 p11/rxd0 si11 note p03 sia0 input serial data input to serial interface input p143 so10 p12 so11 note p02 soa0 output serial data output from serial interface input p144 sck10 p10/txd0 sck11 note p04 scka0 i/o clock input/output for serial interface input p142 ssi11 note input serial interface chip select input input p05/ti001 busy0 input serial interface busy input input p141/buz/intp7 stb0 output serial interface strobe output input p145 rxd0 p11/si10 rxd6 input serial data input to asynchronous serial interface input p14 txd0 p10/sck10 txd6 output serial data output from asynchronous serial interface input p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to capture registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 note external count clock input to 16-bit timer/event counter 01 capture trigger input to capture registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 note ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 note input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input p06/to01 note to00 16-bit timer/event counter 00 output p01/ti010 to01 note output 16-bit timer/event counter 01 output input p06/ti011 note ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input p33/to51/intp4 to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input p16/intp5 note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 44 (2) non-port pins (2/2) pin name i/o function after reset alternate function pcl output clock output (for trimming of x1 input clock, subsystem clock) input p140/intp6 buz output buzzer output input p141/intp7/busy0 ad0 to ad7 i/o lower address/data bus for external memory expansion input p40 to p47 a8 to a15 output higher address bus for external memory expansion input p50 to p57 rd output strobe signal output for external memory read operation input p64 wr output strobe signal output for external memory write operation input p65 wait input wait insertion on external memory access input p66 astb output strobe output that externally latches address information output to ports 4 and 5 for access to external memory input p67 ani0 to ani7 input a/d converter analog input input p20 to p27 av ref input a/d converter reference voltage input ?? av ss ? a/d converter ground potential. make the same potential as ev ss or v ss . ?? kr0 to kr7 input key interrupt input input p70 to p77 regc ? connecting regulator output stabilization capacitor. when using the regulator, connect to v ss via a 0.1 f capacitor. when the regulator is not used, connect directly to v dd . ?? reset input system reset input ?? x1 input ?? x2 ? connecting crystal resonator for x1 input clock oscillation ?? xt1 input ?? xt2 ? connecting crystal resonator for subsystem clock oscillation ?? v dd ? positive power supply (except for ports) ?? ev dd ? positive power supply for ports ?? v ss ? ground potential (except for ports) ?? ev ss ? ground potential for ports ?? ic ? internally connected. connect directly to ev ss or v ss . ?? v pp ? flash memory programming mode setting. high-voltage application for program write/verify. connect directly to ev ss or v ss in normal operation mode. ??
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 45 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 function as a 7-bit i/o port. these pins also function as timer i/o, serial interface data i/o, clock i/o, and chip select input. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as a 7-bit i/o port. p00 to p06 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o. (a) ti000, ti001 note these are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 note these are the pins for inputting a capture trigger signal to the capture register (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 note these are timer output pins. (d) si11 note , so11 note these are serial interface serial data i/o pins. (e) sck11 note this is the serial interface serial clock i/o pin. (f) ssi11 note this is the serial interface chip select input pin. note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins also function as pins for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1).
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 46 (2) control mode p10 to p17 function as external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. (a) si10, so10 these are serial interface serial data i/o pins. (b) sck10 this is the serial interface serial clock i/o pin. (c) rxd0, rxd6, txd0, and txd6 these are the serial data i/o pins of the asynchronous serial interface. (d) ti50 this is the pin for inputting an external count clock to 8-bit timer/event counter 50. (e) to50, toh0, and toh1 these are timer output pins. (f) intp5 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit input-only port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit input-only port. (2) control mode p20 to p27 function as a/d converter analog input pins (ani0 to ani7). 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for external interrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interrupt request input pins and timer i/o pins. (a) intp1 to intp4 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 47 (b) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (c) to51 this is a timer output pin. 2.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. these pins also function as address/data bus pins. the following operation modes can be specified in 1-bit units. (1) port mode p40 to p47 function as an 8-bit i/o port. p40 to p47 can be set to input or output in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). (2) control mode p40 to p47 function as the pins for the lower address/data bus (ad0 to ad7) in external memory expansion mode. 2.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. these pins also function as address bus pins. the following operation modes can be specified in 1-bit units. (1) port mode p50 to p57 function as an 8-bit i/o port. p50 to p57 can be set to input or output in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). (2) control mode p50 to p57 function as the pins for the higher address bus (a8 to a15) in external memory expansion mode. 2.2.7 p60 to p67 (port 6) p60 to p67 function as an 8-bit i/o port. these pins also function as control pins in external memory expansion mode. the following operation modes can be specified in 1-bit units. (1) port mode p60 to p67 function as an 8-bit i/o port. p60 to p67 can be set to input port or output port in 1-bit units using port mode register 6 (pm6). p60 to p63 are n-ch open-drain pins. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. use of an on-chip pull-up resistor can be specified for p64 to p67 by pull-up resistor option register 6 (pu6). (2) control mode p64 to p67 function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. caution p66 functions as an i/o port if the external wait is not used in external memory expansion mode.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 48 2.2.8 p70 to p77 (port 7) p70 to p77 function as an 8-bit i/o port. these pins also function as key interrupt input pins. the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an 8-bit i/o port. p70 to p77 can be set to input or output in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input pins. 2.2.9 p120 (port 12) p120 functions as a 1-bit i/o port. this pin also functions as a pin for external interrupt request input. the following operation modes can be specified. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to input or output using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 functions as an external interrupt request input pin (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.10 p130 (port 13) p130 functions as a 1-bit output-only port. 2.2.11 p140 to p145 (port 14) p140 to p145 function as a 6-bit i/o port. these pins also function as external interrupt request input, clock output, buzzer output, serial interface data i/o, clock i/o, busy input, and strobe output pins. the following operation modes can be specified in 1-bit units. (1) port mode p140 to p145 function as a 6-bit i/o port. p140 to p145 can be set to input or output in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 to p145 function as external interrupt request input, clock output, buzzer output, serial interface data i/o, clock i/o, busy input, and strobe output pins. (a) intp6, intp7 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pcl this is a clock output pin.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 49 (c) buz this is a buzzer output pin. (d) sia0, soa these are serial interface serial data i/o pins. (e) scka0 this is the serial interface serial clock i/o pin. (f) busy0 this is the serial interface busy input pin. (g) stb0 this is the serial interface strobe output pin. 2.2.12 av ref this is the a/d converter reference voltage input pin. when a/d converter is not used, connect this pin to v dd . 2.2.13 av ss this is the a/d converter ground potential pin. even when the a/d converter is not used, always use this pin with the same potential as the ev ss pin or v ss pin. 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting the capacitor for the regulator. when using the regulator, connect this pin to v ss via a 0.1 f capacitor. when the regulator is not used, connect this pin directly to v dd and use it with the same potential as v dd pin. 2.2.16 x1 and x2 these are the pins for connecting a crystal resonator for x1 input clock oscillation. when supplying an external clock, input a signal to the x1 pin and input the inverse signal to the x2 pin. 2.2.17 xt1 and xt2 these are the pins for connecting a crystal resonator for subsystem clock oscillation. when supplying an external clock, input a signal to the xt1 pin and input the inverse signal to the xt2 pin. 2.2.18 v dd and ev dd v dd is the positive power supply pin for other than ports. ev dd is the positive power supply pin for ports. 2.2.19 v ss and ev ss v ss is the ground potential pin for other than ports. ev ss is the ground potential pin for ports.
chapter 2 pin functions preliminary user?s manual u15947ej1v1ud 50 2.2.20 v pp (flash memory versions only) this is a pin for flash memory programming mode setting and high-voltage application for program write/verify. connect directly to ev ss or v ss in the normal operation mode. 2.2.21 ic (mask rom versions only) the ic (internally connected) pin is provided to set the test mode to check the 78k0/kf1 series at shipment. connect it directly to ev ss or v ss pin with the shortest possible wire in the normal operation mode. when a potential difference is produced between the ic pin and the ev ss or v ss pin because the wiring between these two pins is too long or external noise is input to the ic pin, the user?s program may not operate normally. ? connect the ic pin directly to ev ss or v ss . as short as possible ic ev ss or v ss
chapter 2 pin functions preliminary user ? s manual u15947ej1v1ud 51 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the types of pin i/o circuits and the recommended connections of unused pins. refer to figure 2-1 for the configuration of the i/o circuit of each type. table 2-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 p02/so11 note p03/si11 note p04/sck11 note p05/ssi11 note /ti001 note p06/ti011 note /to01 note p10/sck10/txd0 note p11/si10/rxd0 note 8-a p12/so10 p13/txd6 5-a p14/rxd6 8-a p15/toh0 5-a p16/toh1/intp5 p17/ti50/to50 8-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0 to p27/ani7 9-c input connect to ev dd or ev ss . p30/intp1 to p32/intp3 p33/ti51/to51/intp4 8-a p40/ad0 to p47/ad7 p50/a8 to p57/a15 5-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p60, p61 (mask rom version) 13-s p60, p61 (flash memory version) 13-r p62, p63 (mask rom version) 13-w p62, p63 (flash memory version) 13-v input: independently connect to ev dd via a resistor. output: leave open. p64/wd p65/wr p66/wait p67/astb 5-a p70/kr0 to p77/kr7 p120/intp0 8-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148.
chapter 2 pin functions preliminary user ? s manual u15947ej1v1ud 52 table 2-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p130 3-c output leave open. p140/pcl/intp6 p141/buz/busy0/intp7 p142/scka0 p143/sia0 8-a p144/soa0 p145/stb 5-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. reset 2 ? xt1 input connect directly to ev dd or v dd . xt2 16 ? leave open. av ref ?? connect directly to ev dd or v dd . av ss ?? connect directly to ev ss or v ss . ic v pp ?? connect directly to ev ss or v ss .
chapter 2 pin functions preliminary user ? s manual u15947ej1v1ud 53 figure 2-1. pin i/o circuit list (1/2) type 3-c type 2 type 8-a type 5-a type 9-c schmitt-triggered input with hysteresis characteristics in pullup enable data output disable ev dd p-ch v dd p-ch in/out n-ch ev dd p-ch n-ch data out in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + ? pullup enable data output disable input enable ev dd p-ch v dd p-ch in/out n-ch data output disable in/out n-ch type 13-r
chapter 2 pin functions preliminary user ? s manual u15947ej1v1ud 54 figure 2-1. pin i/o circuit list (2/2) type 13-v type 13-s type 13-w type 16 data output disable in/out n-ch ev dd mask option ? ? ? ? ? ? data output disable in/out n-ch input enable middle-voltage input buffer data output disable in/out n-ch ev dd mask option ? ? ? ? ? ? input enable middle-voltage input buffer p-ch feedback cut-off xt1 xt2
preliminary user?s manual u15947ej1v1ud 55 chapter 3 cpu architecture 3.1 memory space products in the 78k0/kf1 series can each access a 64 kb memory space. figures 3-1 to 3-5 show the memory maps. caution regardless of the internal memory capacity, the initial values of the internal memory size switching register (ims) and internal expansion ram size switching register (ixs) of all products in the 78k0/kf1 series are fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. table 3-1. set values of internal memory size switching register (ims) and internal expansion ram size switching register (ixs) ims ixs pd780143 c6h pd780144 c8h 0ch pd780146 cch pd780148 cfh 0ah pd78f0148 value corresponding to mask rom version
chapter 3 cpu architecture preliminary user?s manual u15947ej1v1ud 56 figure 3-1. memory map ( pd780143) ffffh ff00h feffh fee0h fedfh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh 6000h 5fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 5fffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area reserved buffer ram 32 8 bits external memory 38912 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 57 figure 3-2. memory map ( pd780144) ffffh ff00h feffh fee0h fedfh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh 8000h 7fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 7fffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved program memory space data memory space vector table area callt table area program area callf entry area program area reserved internal rom 32768 8 bits buffer ram 32 8 bits external memory 30720 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 58 figure 3-3. memory map ( pd780146) ffffh ff00h feffh fee0h fedfh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh c000h bfffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh bfffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 49152 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area buffer ram 32 8 bits external memory 13312 8 bits reserved internal expansion ram 1024 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 59 figure 3-4. memory map ( pd780148) ffffh ff00h feffh fee0h fedfh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh f000h efffh efffh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area buffer ram 32 8 bits external memory 1024 8 bits internal expansion ram 1024 8 bits reserved
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 60 figure 3-5. memory map ( pd78f0148) ffffh ff00h feffh fee0h fedfh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh f000h efffh efffh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area buffer ram 32 8 bits external memory 1024 8 bits internal expansion ram 1024 8 bits reserved
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 61 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/kf1 series products incorporate internal rom (or flash memory), as shown below. table 3-2. internal memory capacity internal rom part number structure capacity pd780143 24576 8 bits (0000h to 5fffh) pd780144 32768 8 bits (0000h to 7fffh) pd780146 49152 8 bits (0000h to bfffh) pd780148 mask rom 61440 8 bits (0000h to efffh) pd78f0148 flash memory 61440 8 bits (0000h to efffh) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the program start addresses for branch upon reset input or generation of each interrupt request are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 3-3. vector table vector table address interrupt source vector table address interrupt source 0020h inttm000 0000h reset input, poc, lvi, clock monitor, wdt 0022h inttm010 0004h intlvi 0024h intad 0006h intp0 0026h intsr0 0008h intp1 0028h intwti 000ah intp2 002ah inttm51 000ch intp3 002ch intkr 000eh intp4 002eh intwt 0010h intp5 0030h intp6 0012h intsre6 0032h intp7 0014h intsr6 0034h intdmu 0016h intst6 0036h intcsi11 note 0018h intcsi10/intst0 0038h inttm001 note 001ah inttmh1 003ah inttm011 note 001ch inttmh0 003ch intacsi 001eh inttm50 note available only in the pd780146, 780148, and 78f0148.
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 62 (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 3.1.2 internal data memory space 78k0/kf1 series products incorporate the following rams. (1) internal high-speed ram the internal high-speed ram is allocated to the area fb00h to feffh in a 1024 8 bits configuration. the 32-byte area fee0h to feffh is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram table 3-4. internal expansion ram capacity part number internal expansion ram pd780143 pd780144 ? pd780146 pd780148 pd78f0148 1024 8 bits (f400h to f7ffh) the internal expansion ram can also be used as a normal data area similar to the internal high-speed ram, as well as a program area in which instructions can be written and executed. 3.1.3 special function register (sfr) area on-chip peripheral hardware special function registers (sfrs) are allocated in the area ff00h to ffffh (refer to table 3-5 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned.
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 63 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of the instruction to be executed next is addressed by the program counter (pc) (for details, refer to 3.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78k0/kf1 series, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. data memory addressing is illustrated in figures 3-6 to 3-10. for details of each addressing mode, refer to 3.4 operand address addressing . figure 3-6. data memory addressing ( pd780143) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh 6000h 5fffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits external memory 38912 8 bits internal rom 24576 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing reserved reserved buffer ram 32 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 64 figure 3-7. data memory addressing ( pd780144) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fa20h fa1fh fa00h f9ffh f800h f7ffh 8000h 7fffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing external memory 30720 8 bits reserved buffer ram 32 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 65 figure 3-8. data memory addressing ( pd780146) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh c000h bfffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 49152 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing external memory 13312 8 bits reserved buffer ram 32 8 bits internal expansion ram 1024 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 66 figure 3-9. data memory addressing ( pd780148) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing internal expansion ram 1024 8 bits external memory 1024 8 bits reserved buffer ram 32 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 67 figure 3-10. data memory addressing ( pd78f0148) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh fa20h fa1fh fa00h f9ffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing internal expansion ram 1024 8 bits external memory 1024 8 bits reserved buffer ram 32 8 bits
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 68 3.2 processor registers the 78k0/kf1 series products incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-11. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-12. format of program status word 70 psw ie z rbs1 ac rbs0 0 isp cy
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 69 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and only non-maskable interrupt requests become acknowledgeable. other interrupt requests are all disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgement is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction execution or interrupt acknowledgement and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (refer to 19.3 (3) priority specification flag registers (pr0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgement is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area.
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 70 figure 3-13. format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores data as shown in figures 3-14 and 3-15. caution since reset input makes the sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-14. data to be saved to stack memory interrupt and brk instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 figure 3-15. data to be restored from stack memory reti and retb instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 71 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-16. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 72 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the special function registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0, and is defined by the header file ? sfrbit.h ? in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input.
chapter 3 cpu architecture preliminary user?s manual u15947ej1v1ud 73 table 3-5. special function register list (1/4) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 r/w ?? 00h ff01h port 1 p1 r/w ?? 00h ff02h port 2 p2 r ?? 00h ff03h port 3 p3 r/w ?? 00h ff04h port 4 p4 r/w ?? 00h ff05h port 5 p5 r/w ?? 00h ff06h port 6 p6 r/w ?? 00h ff07h port 7 p7 r/w ?? 00h ff08h ff09h a/d conversion result register adcr r ?? undefined ff0ah receive buffer register 6 rxb6 r ?? ffh ff0bh transmit buffer register 6 txb6 r/w ?? ffh ff0ch port 12 p12 r/w ?? 00h ff0dh port 13 p13 r/w ?? 00h ff0eh port 14 p14 r/w ?? 00h ff0fh serial i/o shift register 10 sio10 r ?? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ?? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ?? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ?? 0000h ff16h 8-bit timer counter 50 tm50 r ?? 00h ff17h 8-bit timer compare register 50 cr50 r/w ?? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ?? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ?? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ?? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ?? 00h ff1fh 8-bit timer counter 51 tm51 r ?? 00h ff20h port mode register 0 pm0 r/w ?? ffh ff21h port mode register 1 pm1 r/w ?? ffh ff23h port mode register 3 pm3 r/w ?? ffh ff24h port mode register 4 pm4 r/w ?? ffh ff25h port mode register 5 pm5 r/w ?? ffh ff26h port mode register 6 pm6 r/w ?? ffh ff27h port mode register 7 pm7 r/w ?? ffh ff28h a/d converter mode register adm r/w ?? 00h ff29h analog input channel specification register ads r/w ?? 00h ff2ah power-fail comparison mode register pfm r/w ?? 00h ff2bh power-fail comparison threshold register pft r/w ?? 00h
chapter 3 cpu architecture preliminary user?s manual u15947ej1v1ud 74 table 3-5. special function register list (2/4) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff2ch port mode register 12 pm12 r/w ?? ffh ff2eh port mode register 14 pm14 r/w ?? ffh ff30h pull-up resistor option register 0 pu0 r/w ?? 00h ff31h pull-up resistor option register 1 pu1 r/w ?? 00h ff33h pull-up resistor option register 3 pu3 r/w ?? 00h ff34h pull-up resistor option register 4 pu4 r/w ?? 00h ff35h pull-up resistor option register 5 pu5 r/w ?? 00h ff36h pull-up resistor option register 6 pu6 r/w ?? 00h ff37h pull-up resistor option register 7 pu7 r/w ?? 00h ff3ch pull-up resistor option register 12 pu12 r/w ?? 00h ff3eh pull-up resistor option register 14 pu14 r/w ?? 00h ff40h clock output selection register cks r/w ?? 00h ff41h 8-bit timer compare register 51 cr51 r/w ?? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ?? 00h ff47h memory expansion mode register mem r/w ?? 00h ff48h external interrupt rising edge enable register egp r/w ?? 00h ff49h external interrupt falling edge enable register egn r/w ?? 00h ff4ah serial i/o shift register 11 note sio11 r ?? 00h ff4ch transmit buffer register 11 note sotb11 r/w ?? undefined ff4fh input switch control register isc r/w ?? 00h ff50h asynchronous serial interface operation mode register 6 asim6 r/w ?? 01h ff53h asynchronous serial interface reception error status register 6 asis6 r ?? 00h ff55h asynchronous serial interface transmission status register 6 asif6 r ?? 00h ff56h clock selection register 6 cksr6 r/w ?? 00h ff57h baud rate generator control register 6 brgc6 r/w ?? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ?? 16h ff60h remainder data register 0 sdr0 sdr0l r ?? 00h ff61h sdr0h ? 00h ff62h multiplication/division data register a0 mda0l mda0ll r/w ?? 00h ff63h mda0lh ? 00h ff64h mda0h mda0hl r/w ?? 00h ff65h mda0hh ? 00h ff66h multiplication/division data register b0 mdb0 mdb0l r/w ?? 00h ff67h mdb0h ? 00h ff68h multiplier/divider control register 0 dmuc0 r/w ?? 00h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ?? 00h ff6ah timer clock selection register 50 tcl50 r/w ?? 00h note pd780146, 780148, and 78f0148 only.
chapter 3 cpu architecture preliminary user?s manual u15947ej1v1ud 75 table 3-5. special function register list (3/4) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff6bh 8-bit timer mode control register 50 tmc50 r/w ?? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ?? 00h ff6dh 8-bit timer h carrier control register 1 tmcyc1 r/w ?? 00h ff6eh key return mode register krm r/w ?? 00h ff6fh watch timer operation mode register wtm r/w ?? 00h ff70h asynchronous serial interface operation mode register 0 asim0 r/w ?? 01h ff71h baud rate generator control register 0 brgc0 r/w ?? 1fh ff72h receive buffer register 0 rxb0 r ?? ffh ff73h asynchronous serial interface reception error status register 0 asis0 r ?? 00h ff74h transmit shift register 0 txs0 w ?? ffh ff80h serial operation mode register 10 csim10 r/w ?? 00h ff81h serial clock selection register 10 csic10 r/w ?? 00h ff84h transmit buffer register 10 sotb10 r/w ?? undefined ff88h serial operation mode register 11 note 1 csim11 r/w ?? 00h ff89h serial clock selection register 11 note 1 csic11 r/w ?? 00h ff8ch timer clock selection register 51 tcl51 r/w ?? 00h ff90h serial operation mode specification register 0 csima0 r/w ?? 00h ff91h serial status register 0 csis0 r/w ?? 00h ff92h serial trigger register 0 csit0 r/w ?? 00h ff93h divisor selection register 0 brgca0 r/w ?? 03h ff94h automatic data transfer address point specification register 0 adtp0 r/w ?? 00h ff95h automatic data transfer interval specification register 0 adti0 r/w ?? 00h ff96h serial i/o shift register 0 sioa0 r/w ?? 00h ff97h automatic data transfer address count register 0 adtc3 r ?? 00h ff98h watchdog timer mode register wdtm r/w ?? 67h ff99h watchdog timer enable register wdte r/w ?? 9ah ffa0h ring-osc mode register rcm r/w ?? 00h ffa1h main clock mode register mcm r/w ?? 00h ffa2h main osc control register moc r/w ?? 00h ffa3h oscillation stabilization time counter status register ostc r ?? 00h ffa4h oscillation stabilization time select register osts r/w ?? 05h ffa9h clock monitor mode register clm r/w ?? 00h ffach reset control flag register resf r ?? 00h note 2 ffb0h ffb1h 16-bit timer counter 01 note 1 tm01 r ?? 0000h notes 1. pd780146, 780148, and 78f0148 only. 2. this value varies depending on the reset source.
chapter 3 cpu architecture preliminary user?s manual u15947ej1v1ud 76 table 3-5. special function register list (4/4) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffb2h ffb3h 16-bit timer capture/compare register 001 note 1 cr001 r/w ?? 0000h ffb4h ffb5h 16-bit timer capture/compare register 011 note 1 cr011 r/w ?? 0000h ffb6h 16-bit timer mode control register 01 note 1 tmc01 r/w ?? 00h ffb7h prescaler mode register 01 note 1 prm01 r/w ?? 00h ffb8h capture/compare control register 01 note 1 crc01 r/w ?? 00h ffb9h 16-bit timer output control register 01 note 1 toc01 r/w ?? 00h ffbah 16-bit timer mode control register 00 tmc00 r/w ?? 00h ffbbh prescaler mode register 00 prm00 r/w ?? 00h ffbch capture/compare control register 00 crc00 r/w ?? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ?? 00h ffbeh low-voltage detection register lvim r/w ?? 00h ffbfh low-voltage detection level selection register lvis r/w ?? 00h ffe0h interrupt request flag register 0l if0 if0l r/w ?? 00h ffe1h interrupt request flag register 0h if0h r/w ? 00h ffe2h interrupt request flag register 1l if1 if1l r/w ?? 00h ffe3h interrupt request flag register 1h if1h r/w ? 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ?? ffh ffe5h interrupt mask flag register 0h mk0h r/w ? ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ?? ffh ffe7h interrupt mask flag register 1h mk1h r/w ? dfh ffe8h priority specification flag register 0l pr0 pr0l r/w ?? ffh ffe9h priority specification flag register 0h pr0h r/w ? ffh ffeah priority specification flag register 1l pr1 pr1l r/w ?? ffh ffebh priority specification flag register 1h pr1h r/w ? ffh fff0h internal memory size switching register note 2 ims r/w ?? cfh fff4h internal ex pansion ram size switching register note 2 ixs r/w ?? 0ch fff8h memory expansion wait setting register mm r/w ?? 10h fffbh processor clock control register pcc r/w ?? 00h notes 1. pd780146, 780148, and 78f0148 only. 2. the default value of ims and ixs are fixed (ims = cfh, ixs = 0ch) in all products in the 78k0/kf1 series regardless of the internal memory capacity. therefore, set the following value to each product. ims ixs pd780143 c6h pd780144 c8h 0ch pd780146 cch pd780148 cfh 0ah pd78f0148 value corresponding to mask rom version
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 77 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two ? s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relative branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 78 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10 ? 8 11 10 00001 643 callf fa 7 ? 0
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 79 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 ? 0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 80 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/kf1 series instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values that become decimal correction targets ror4/rol4 a register for storage of digit data that undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 81 3.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register bank select flags (rbs0 to rbs1) and the register specify codes (rn and rpn) of an operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ? r ? and ? rp ? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 82 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 83 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing sfrs to be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] shown below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (s addr-offset) 01010000 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 84 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 85 3.4.6 register indirect addressing [function] register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 86 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
chapter 3 cpu architecture preliminary user ? s manual u15947ej1v1ud 87 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] in the case of push de operation code 10110101
preliminary user?s manual u15947ej1v1ud 88 chapter 4 port functions 4.1 port functions 78k0/kf1 series products are provided with the ports shown in figure 4-1, which enable variety of control operations. the functions of each port are shown in table 4-1. in addition to the function as digital i/o ports, these ports have several alternate functions. for details of the alternate functions, refer to chapter 2 pin functions . figure 4-1. port types port 2 p20 p27 port 3 p30 p33 port 5 p50 p57 port 0 p00 p06 port 1 p10 p17 port 4 p40 p47 port 6 p60 p67 port 7 p70 p77 p120 port 12 port 14 p140 p145 p130 port 13
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 89 table 4-1. port functions (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ad0 to ad7 p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input a8 to a15 note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148.
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 90 table 4-1. port functions (2/2) pin name i/o function after reset alternate function p60 to p63 n-ch open-drain i/o port. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. ? p64 rd p65 wr p66 wait p67 i/o port 6. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input astb p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input kr0 to kr7 p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? p140 pcl/intp6 p141 buz/busy0/ intp7 p142 scka0 p143 sia0 p144 soa0 p145 i/o port 14. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input stb0 4.2 port configuration ports consist of the following hardware. table 4-2. port configuration item configuration control registers port mode register (pm0, pm1, pm3 to pm7, pm12, pm14) pull-up resistor option register (pu0, pu1, pu3 to pu7, pu12, pu14) input switch control register (isc) port total: 67 (cmos i/o: 54, cmos input: 8, cmos output: 1, n-ch open drain output: 4) pull-up resistor ? mask rom version total: 58 (software control: 54, mask option specification: 4) ? flash memory version: total: 54
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 91 4.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o, serial interface data i/o, and clock i/o. reset input sets port 0 to input mode. figures 4-2 to 4-5 show block diagrams of port 0. caution when p02/so11 note , p03/si11 note , and p04/sck11 note are used as general-purpose ports, do not write to serial clock selection register 11 (csic11). figure 4-2. block diagram of p00, p03, and p05 p00/ti000, p03/si11 note , p05/ssi11 note /ti001 note wr pu rd wr port wr pm pu00, pu03, pu05 alternate function output latch (p00, p03, p05) pm00, pm03, pm05 ev dd p-ch selector internal bus note available only in the pd780146, 780148, and 78f0148. pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 92 figure 4-3. block diagram of p01 and p06 p01/ti010/to00, p06/ti011 note /to01 note wr pu rd wr port wr pm pu01, pu06 alternate function output latch (p01, p06) pm01, pm06 alternate function ev dd p-ch selector internal bus note available only in the pd780146, 780148, and 78f0148. pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 93 figure 4-4. block diagram of p02 p02/so11 note wr pu rd wr port wr pm pu02 output latch (p02) pm02 alternate function ev dd p-ch selector internal bus note available only in the pd780146, 780148, and 78f0148. pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 94 figure 4-5. block diagram of p04 p04/sck11 note wr pu rd wr port wr pm pu04 alternate function output latch (p04) pm04 alternate function ev dd p-ch selector internal bus note available only in the pd780146, 780148, and 78f0148. pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 95 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. reset input sets port 1 to input mode. figures 4-6 to 4-11 show block diagrams of port 1. caution when p10/sck10/txd0, p11/si10/rxd0, and p12/so10 are used as general-purpose ports, do not write to serial clock selection register 10 (csic10). figure 4-6. block diagram of p10 p10/sck10/txd0 wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function ev dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 96 figure 4-7. block diagram of p11 and p14 p11/si10/rxd0, p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 97 figure 4-8. block diagram of p12 p12/so10 wr pu rd wr port wr pm pu12 output latch (p12) pm12 alternate function ev dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 98 figure 4-9. block diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function ev dd p-ch internal bus selector pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 99 figure 4-10. block diagram of p15 p15/toh0 wr pu rd wr port wr pm pu15 output latch (p15) pm15 alternate function ev dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 100 figure 4-11. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function ev dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 101 4.2.3 port 2 port 2 is an 8-bit input-only port. this port can also be used for a/d converter analog input. figure 4-12 shows a block diagram of port 2. figure 4-12. block diagram of p20 to p27 v ref rd a/d converter p20/ani0 to p27/ani7 + ? internal bus rd: port 2 read signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 102 4.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input. reset input sets port 3 to input mode. figures 4-13 and 4-14 show block diagrams of port 3. figure 4-13. block diagram of p30 to p32 p30/intp1 to p32/intp3 wr pu rd wr port wr pm pu30 to pu32 alternate function output latch (p30 to p32) pm30 to pm32 ev dd p-ch selector internal bus pu3: pull-up resistor option register 3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 103 figure 4-14. block diagram of p33 p33/intp4/ti51/to51 wr pu rd wr port wr pm pu33 alternate function output latch (p33) pm33 alternate function ev dd p-ch selector internal bus pu0: pull-up resistor option register 3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 104 4.2.5 port 4 port 4 is an 8-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (pu4). this port can also be used as an address/data bus in external memory expansion mode. reset input sets port 4 to input mode. figure 4-15 shows a block diagram of port 4. figure 4-15. block diagram of p40 to p47 rd p-ch wr pu wr port wr pm ev dd p40/ad0 to p47/ad7 pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector internal bus alternate function selector memory expansion mode register (mem) alternate function pu: pull-up resistor option register pm: port mode register rd: port 4 read signal wr: port 4 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 105 4.2.6 port 5 port 5 is an 8-bit i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (pu5). this port can also be used as an address bus in external memory expansion mode. reset input sets port 5 to input mode. figure 4-16 shows a block diagram of port 5. figure 4-16. block diagram of p50 to p57 rd p-ch wr pu wr port wr pm ev dd p50/a8 to p57/a15 pu50 to pu57 output latch (p50 to p57) pm50 to pm57 selector internal bus alternate function selector memory expansion mode register (mem) pu: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 106 4.2.7 port 6 port 6 is an 8-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). this port has the following functions for pull-up resistors. these functions differ depending on the higher 4 bits/lower 4 bits of the port, and whether the product is a mask rom version or a flash memory version. table 4-3. pull-up resistor of port 6 higher 4 bits (pins p64 to p67) lower 4 bits (pins p60 to p63) mask rom version an on-chip pull-up resistor can be specified in 1-bit units by mask option flash memory version an on-chip pull-up resistor can be connected in 1-bit units by pu6 on-chip pull-up resistors are not provided pu6: pull-up resistor option register 6 the p64 to p67 pins can also be used for the control signal output function in external memory expansion mode. reset input sets port 6 to input mode. figures 4-17 to 4-19 show block diagrams of port 6. caution p66 can be used as an i/o port when an external wait is not used in external memory expansion mode. figure 4-17. block diagram of p60 to p63 rd p60 to p63 wr port wr pm output latch (p60 to p63) pm60 to pm63 selector ev dd mask option resistor ? ? ? ? ? ? ? ? ? ? internal bus mask rom versions only no pull-up resistor for flash memory versions pm: port mode register rd: port 6 read signal wr: port 6 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 107 figure 4-18. block diagram of p64, p65, and p67 rd p64/rd, p65/wr, p67/astb p-ch wr pu wr port wr pm pu64, pu65, pu67 pm64, pm65, pm67 ev dd output latch (p64, p65, p67) selector internal bus alternate function selector memory expansion mode register (mem) pu6: pull-up resistor option register 6 pm: port mode register rd: port 6 read signal wr: port 6 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 108 figure 4-19. block diagram of p66 rd p66/wait p-ch wr pu wr port wr pm pu66 pm66 ev dd output latch (p66) selector internal bus alternate function selector memory expansion mode register (mem) pu6: pull-up resistor option register 6 pm: port mode register rd: port 6 read signal wr: port 6 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 109 4.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). this port can also be used for key return input. reset input sets port 7 to input mode. figure 4-20 shows a block diagram of port 7. figure 4-20. block diagram of p70 to p77 p70/kr0 to p77/kr7 wr pu rd wr port wr pm pu70 to pu77 alternate function output latch (p70 to p77) pm70 to pm77 ev dd p-ch selector internal bus pu7: pull-up resistor option register 7 pm: port mode register rd: port 7 read signal wr: port 7 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 110 4.2.9 port 12 port 12 is a 1-bit i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used for external interrupt input. reset input sets port 12 to input mode. figure 4-21 shows a block diagram of port 12. figure 4-21. block diagram of p120 p120/intp0 wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch selector internal bus pu12: pull-up resistor option register 12 pm: port mode register rd: port 12 read signal wr: port 12 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 111 4.2.10 port 13 port 13 is a 1-bit output-only port. figure 4-22 shows a block diagram of port 13. figure 4-22. block diagram of p130 rd output latch (p130) wr port p130 internal bus rd: port 13 read signal wd: port 13 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 112 4.2.11 port 14 port 14 is a 6-bit i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 to p145 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). this port can also be used for external interrupt request input, serial interface data i/o, clock i/o, busy input, buzzer output, and clock output. reset input sets port 14 to input mode. figures 4-23 to 4-26 show block diagrams of port 14. figure 4-23. block diagram of p140 and p141 p140/pcl/intp6, p141/buz/busy0/intp7 wr pu rd wr port wr pm pu140, pu141 alternate function output latch (p140, p141) pm140, pm141 alternate function ev dd p-ch selector internal bus pu14: pull-up resistor option register 14 pm: port mode register rd: port 14 read signal wr: port 14 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 113 figure 4-24. block diagram of p142 p142/scka0 wr pu rd wr port wr pm pu142 alternate function output latch (p142) pm142 alternate function ev dd p-ch selector internal bus pu14: pull-up resistor option register 14 pm: port mode register rd: port 14 read signal wr: port 14 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 114 figure 4-25. block diagram of p143 p143/sia0 wr pu rd wr port wr pm pu143 alternate function output latch (p143) pm143 ev dd p-ch selector internal bus pu14: pull-up resistor option register 14 pm: port mode register rd: port 14 read signal wr: port 14 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 115 figure 4-26. block diagram of p144 and p145 p144/soa0, p145/stb0 wr pu rd wr port wr pm pu144, pu145 output latch (p144, p145) pm144, pm145 alternate function ev dd p-ch selector internal bus pu14: pull-up resistor option register 14 pm: port mode register rd: port 14 read signal wr: port 14 write signal
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 116 4.3 registers controlling port function port functions are controlled by the following three types of registers. ? port mode registers (pm0, pm1, pm3 to pm7, pm12, pm14) ? pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu14) ? input switch control register (isc) (1) port mode registers (pm0, pm1, pm3 to pm7, pm12, and pm14) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch as shown in table 4-4. figure 4-27. format of port mode register 7 1 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 ff21h ffh r/w 7 1 pm3 6 1 5 1 4 1 3 pm33 2 pm32 1 pm31 0 pm30 ff23h ffh r/w 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 ff24h ffh r/w 7 pm57 pm5 6 pm56 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 ff25h ffh r/w 7 pm67 pm6 6 pm66 5 pm65 4 pm64 3 pm63 2 pm62 1 pm61 0 pm60 ff26h ffh r/w 7 pm77 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 ff27h ffh r/w 7 1 pm12 6 1 5 1 4 1 3 1 2 1 1 1 0 pm120 ff2ch ffh r/w 7 1 pm14 6 1 5 pm145 4 pm144 3 pm143 2 pm142 1 pm141 0 pm140 ff2eh ffh r/w pmmn pmn pin i/o mode selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 117 table 4-4. settings of port mode register and output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 p02 so11 note output 0 0 p03 si11 note input 1 input 1 p04 sck11 note output 0 1 ssi11 note input 1 p05 ti001 note input 1 ti011 note input 1 p06 to01 note output 0 0 input 1 sck10 output 0 1 p10 txd0 output 0 1 si10 input 1 p11 rxd0 input 1 p12 so10 output 0 0 p13 txd6 output 0 1 p14 rxd6 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 p30 to p32 intp1 to intp3 input 1 intp4 input 1 ti51 input 1 p33 to51 output 0 0 input 1 p40 to p47 ad0 to ad7 output 0 0 p50 to p57 a8 to a15 output 0 0 note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148. remark :don ? t care pm : port mode register p : port output latch
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 118 table 4-4. settings of port mode register and output latch when using alternate function (2/2) alternate function pin name function name i/o pm p p64 rd output 0 0 p65 wr output 0 0 p66 wait input 1 p67 astb output 0 0 p70 to p77 kr0 to kr7 input 1 p120 intp0 input 1 pcl output 0 0 p140 intp6 input 1 buz output 0 0 busy0 input 1 p141 intp7 input 1 input 1 p142 scka0 output 0 1 p143 sia0 input 1 p144 soa0 output 0 0 p145 stb0 output 0 0 remark :don ? t care pm : port mode register p : port output latch
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 119 (2) pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, and pu14) these registers specify whether the on-chip pull-up resistors of p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, or p140 to p145 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. on-chip pull-up resistors cannot be used for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of pu0, pu1, pu3 to pu7, pu12, and pu14. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution use of a pull-up resistor can be specified for p60 to p63 pins by a mask option only in the mask rom versions. figure 4-28. format of pull-up resistor option register 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w 7 pu17 pu1 6 pu16 5 pu15 4 pu14 3 pu13 2 pu12 1 pu11 0 pu10 ff31h 00h r/w 7 0 pu3 6 0 5 0 4 0 3 pu33 2 pu32 1 pu31 0 pu30 ff33h 00h r/w 7 pu47 pu4 6 pu46 5 pu45 4 pu44 3 pu43 2 pu42 1 pu41 0 pu40 ff34h 00h r/w 7 pu57 pu5 6 pu56 5 pu55 4 pu54 3 pu53 2 pu52 1 pu51 0 pu50 ff35h 00h r/w 7 pu67 pu6 6 pu66 5 pu65 4 pu64 3 0 2 0 1 0 0 0 ff36h 00h r/w 7 pu77 pu7 6 pu76 5 pu75 4 pu74 3 pu73 2 pu72 1 pu71 0 pu70 ff37h 00h r/w 7 0 pu12 6 0 5 0 4 0 3 0 2 0 1 0 0 pu120 ff3ch 00h r/w 7 0 pu14 6 0 5 pu145 4 pu144 3 pu143 2 pu142 1 pu141 0 pu140 ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 120 (3) input switch control register (isc) this register is used to receive a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. for the port configuration during lin reception, refer to figure 15-3 port configuration for lin reception operation in chapter 15 serial interface uart6 . this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 4-29. format of input switch control register (isc) address: ff4fh after reset: 00h r/w symbol76543210 isc000000isc1isc0 isc1 input signal selection 0 ti000 input 1 rxd6 input isc0 input signal selection 0 intp0 input 1 rxd6 input
chapter 4 port functions preliminary user ? s manual u15947ej1v1ud 121 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit. 4.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
preliminary user?s manual u15947ej1v1ud 122 chapter 5 external bus interface 5.1 external bus interface the external bus interface connects external devices to areas other than the internal rom, ram, and sfr areas. connection of external devices uses ports 4 to 6. ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. the external bus interface is usable only when the x1 clock is selected as the cpu clock. table 5-1. pin functions in external memory expansion mode pin function when external device is connected name function alternate function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 5-2. state of ports 4 to 6 pins in external memory expansion mode port 4 port 5 port 6 external expansion mode port 0 to 7 0123456701234567 single-chip mode port port port 256-byte expansion mode address/data port port rd, wr, wait, astb 4 kb expansion mode address/data address port port rd, wr, wait, astb 16 kb expansion mode address/data address port port rd, wr, wait, astb full-address mode address/data address port rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port in all modes.
chapter 5 external bus interface preliminary user?s manual u15947ej1v1ud 123 the memory maps when the external bus interface is used are as follows. figure 5-1. memory map when using external bus interface (1/2) (a) memory map of pd780143 and of pd78f0148 when internal rom (flash memory) size is 24 kb (b) memory map of pd780144 and of pd78f0148 when internal rom (flash memory) size is 32 kb sfr internal high-speed ram buffer ram full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh ff00h feffh fb00h faffh f800h f7ffh a000h 9fffh 7000h 6fffh 6100h 60ffh 6000h 5fffh 0000h ffffh ff00h feffh fb00h faffh f800h f7ffh c000h bfffh 9000h 8fffh 8100h 80ffh 8000h 7fffh 0000h sfr internal high-speed ram buffer ram full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode fa20h fa1fh fa00h f9ffh reserved reserved reserved reserved fa20h fa1fh fa00h f9ffh
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 124 figure 5-1. memory map when using external bus interface (2/2) (c) memory map of pd780146 and of pd78f0148 when internal rom (flash memory) size is 48 kb (d) memory map of pd780148 and of pd78f0148 when internal rom (flash memory) size is 60 kb sfr internal high-speed ram buffer ram full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh ff00h feffh fa20h fa1fh f800h f7ffh f400h f3ffh c100h c0ffh 0000h d000h cfffh c000h bfffh 4 kb expansion mode (when mm2 to mm0 = 100) ffffh ff00h feffh fa20h fa1fh f800h f7ffh fa00h f9ffh f100h f0ffh 0000h f400h f3ffh f000h efffh sfr internal high-speed ram buffer ram full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) or 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode reserved reserved internal expansion ram fb00h faffh fa00h f9ffh reserved reserved internal expansion ram fb00h faffh
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 125 5.2 registers controlling external bus interface the external bus interface is controlled by the following two registers. ? memory expansion mode register (mem) ? memory expansion wait setting register (mm) (1) memory expansion mode register (mem) mem sets the external expansion area. mem is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mem to 00h. figure 5-2. format of memory expansion mode register (mem) address: ff47h after reset: 00h r/w symbol76543210 mem00000mm2mm1mm0 p40 to p47, p50 to p57, p64 to p67 pin state mm2 mm1 mm0 single-chip/memory expansion mode selection p40 to p47 p50 to p53 p54, p55 p56, p57 p64 to p67 0 0 0 single-chip mode port mode 011 256-byte mode port mode 100 4 kb mode port mode 1 0 1 16 kb mode port mode 111 memory expansion mode full-address mode note ad0 to ad7 a8 to a11 a12, a13 a14, a15 p64 = rd p65 = wr p66 = wait p67 = astb other than above setting prohibited note the full-address mode allows external expansion to the entire 64 kb address space except for the internal rom, ram, sfr areas and the reserved areas.
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 126 (2) memory expansion wait setting register (mm) mm sets the number of waits. mm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 5-3. format of memory expansion wait setting register (mm) address: fff8h after reset: 10h r/w symbol76543210 mm 00pw1pw00000 pw1 pw0 wait control 0 0 no wait 0 1 wait (one wait state inserted) 1 0 setting prohibited 1 1 wait control by external wait pin caution to control wait with external wait pin, be sure to set wait/p66 pin to input mode (set bit 6 (pm66) of port mode register 6 (pm6) to 1).
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 127 5.3 external bus interface function timing timing control signal output pins in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output in data access and instruction fetch from external memory. during internal memory access, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output in data access to external memory. during internal memory access, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an i/o port. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. the address strobe signal is output regardless of data access and instruction fetch from external memory. during internal memory access, the address strobe signal is output. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pins. valid signal is output or input during data accesses and instruction fetches from external memory. these signals change even during internal memory access (output values are undefined). the timing charts are shown in figures 5-4 to 5-7.
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 128 figure 5-4. instruction fetch from external memory (a) no wait (pw1, pw0 = 0, 0) setting rd astb ad0 to ad7 a8 to a15 lower address instruction code higher address (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address instruction code higher address (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 wait lower address instruction code higher address
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 129 figure 5-5. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting rd astb ad0 to ad7 a8 to a15 lower address read data higher address (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address read data higher address (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 wait lower address read data higher address
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 130 figure 5-6. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting wr astb ad0 to ad7 a8 to a15 lower address write data higher address hi-z (b) wait (pw1, pw0 = 0, 1) setting wr astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address write data higher address hi-z (c) external wait (pw1, pw0 = 1, 1) setting wr astb ad0 to ad7 a8 to a15 wait lower address write data higher address hi-z
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 131 figure 5-7. external memory read modify write timing (a) no wait (pw1, pw0 = 0, 0) setting read data write data higher address hi-z lower address rd astb ad0 to ad7 a8 to a15 wr (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 hi-z wr write data higher address internal wait signal (1-clock wait) read data lower address (c) external wait (pw1, pw0 = 1, 1) setting wait hi-z rd astb ad0 to ad7 a8 to a15 wr write data higher address read data lower address
chapter 5 external bus interface preliminary user ? s manual u15947ej1v1ud 132 5.4 example of connection with memory an example of connecting the pd780143 with external memory (in this example, sram) is shown in figure 5-8. in addition, the external bus interface function is used in the full-address mode, and the addresses from 0000h to 7fffh (32 kb) are allocated to internal rom, and the addresses after 8000h to sram. figure 5-8. connection example of pd780143 and memory rd wr a8 to a14 astb ad0 to ad7 v dd 74hc573 le d0 to d7 oe q0 to q7 pd43256b cs oe we i/o1 to i/o8 a0 to a14 data bus pd780143 address bus
preliminary user?s manual u15947ej1v1ud 133 chapter 6 clock generator 6.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three system clock oscillators are available. ? x1 oscillator the x1 oscillator oscillates a clock of 2.0 to 10.0 mhz. oscillation can be stopped by executing the stop instruction or setting the main osc control register (moc) and processor clock control register (pcc). ? ring-osc oscillator the ring-osc oscillator oscillates a clock of 240 khz (typ.). oscillation can be stopped by setting the ring- osc mode register (rcm) when ?can be stopped by software? is set by a mask option and the x1 input clock is used as the cpu clock. ? subsystem clock oscillator the subsystem clock oscillator oscillates a clock of 32.768 khz. oscillation cannot be stopped. when subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the processor clock control register (pcc), and the power consumption can be reduced in the stop mode. 6.2 configuration of clock generator the clock generator consists of the following hardware. table 6-1. configuration of clock generator item configuration control registers processor clock control register (pcc) ring-osc mode register (rcm) main clock mode register (mcm) main osc control register (moc) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillator x1 oscillator ring-osc oscillator subsystem clock oscillator
chapter 6 clock generator preliminary user?s manual u15947ej1v1ud 134 figure 6-1. block diagram of clock generator x1 x2 f xp f xt frc xt1 xt2 f x 2 2 stop mstop f x 2 3 f x 2 4 f x 2 4 rstop css pcc2 cls mcm0 mcs cls mcc osts1 osts0 osts2 1/2 3 most 16 most 15 most 14 most 13 most 11 c p u f r f x pcc1 pcc0 x1 oscillator internal bus ring-osc mode register (rcm) main osc control register (moc) internal bus ring-osc oscillator mask option 1: cannot be stopped 0. can be stopped cpu clock (f cpu ) controller processor clock control register (pcc) main clock mode register (mcm) x1 oscillation stabilization time counter oscillation stabilization time select register (osts) oscillation stabilization time counter status register (ostc) clock to peripheral hardware prescaler operation clock switch 8-bit timer h1, watchdog timer prescaler prescaler selector subsystem clock oscillator watch clock, clock output function
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 135 6.3 registers controlling clock generator the following six registers are used to control the clock generator. ? processor clock control register (pcc) ? ring-osc mode register (rcm) ? main clock mode register (mcm) ? main osc control register (moc) ? oscillation stabilization time counter status register (ostc) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) the pcc register is used to select the cpu clock, the division ratio, main system clock oscillator operation/stop and whether to use the on-chip feedback resistor of the subsystem clock oscillator. the pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears pcc to 00h. figure 6-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 136 figure 6-3. format of processor clock control register (pcc) address: fffbh after reset: 00h r/w note 1 symbol 76543210 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc control of x1 oscillator operation note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock feedback resistor selection note 3 0 on-chip feedback resistor used 1 on-chip feedback resistor not used cls cpu clock status 0 x1 input clock or ring-osc clock 1 subsystem clock css note 4 pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 000f x 001f x /2 010f x /2 2 011f x /2 3 0 100f x /2 4 000 001 010 011 1 100 f xt /2 other than above setting prohibited notes 1. bit 5 is read-only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the x1 oscillator operation. when the cpu is operating on the ring-osc clock, use bit 7 (mstop) of the main osc control register (moc) to stop the x1 oscillator operation (this cannot be set by mcc). a stop instruction should not be used. 3. the feedback resistor is required to adjust the bias point of the oscillation waveform to close to the middle of the power supply voltage. setting frc to 1 can further reduce the current consumption in the stop mode, but only when the subsystem clock is not used. 4. be sure to switch css from 1 to 0 when bits 1 (mcs) and 0 (mcm0) of the main clock mode register (mcm) are 1. caution be sure to set bit 3 to 0. remarks 1. f x : main system clock oscillation frequency (x1 input clock oscillation frequency or ring-osc clock oscillation frequency) 2. f xt : subsystem clock oscillation frequency
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 137 the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k0/kf1 series. therefore, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in the table 6-2. table 6-2. relationship between cpu clock and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) x1 input clock note (at 10 mhz operation) ring-osc clock note (at 240 khz (typ.) operation) subsystem clock (at 32.768 khz operation) f x 0.2 s8.3 s (typ.) ? f x /2 0.4 s 16.6 s (typ.) ? f x /2 2 0.8 s 33.2 s (typ.) ? f x /2 3 1.6 s 66.4 s (typ.) ? f x /2 4 3.2 s 132.8 s (typ.) ? f xt /2 ?? 122.1 s note the main clock mode register (mcm) is used to set the cpu clock (x1 input clock/ring-osc clock) (see figure 6-5 ). (2) ring-osc mode register (rcm) this register sets the operation mode of ring-osc. this register is valid when ? can be stopped by software ? is set for ring-osc by a mask option, and the x1 input clock or subsystem clock is selected as the cpu clock. if ? cannot be stopped ? is selected for ring-osc by a mask option, settings for this register are invalid. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 6-4. format of ring-osc mode register (rcm) address : ffa0h after reset : 00h r/w symbol 76543210 rcm0000000rstop rstop ring-osc oscillating/stopped 0 ring-osc oscillating 1 ring-osc stopped caution make sure that the bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting rstop.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 138 (3) main clock mode register (mcm) this register sets the cpu clock (x1 input clock/ring-osc clock). mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 6-5. format of main clock mode register (mcm) address : ffa1h after reset : 00h r/w symbol 76543210 mcm 0 0 0 0 0 0 mcs mcm0 mcs cpu clock status 0 operates with ring-osc clock 1 operates with x1 input clock mcm0 selection of clock supplied to cpu 0 ring-osc clock 1 x1 input clock cautions 1. when ring-osc clock is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hardware with ring-osc clock cannot be guaranteed. therefore, when ring-osc clock is selected as the clock supplied to the cpu, do not use peripheral hardware. in addition, stop the peripheral hardware before switching the clock supplied to the cpu from the x1 input clock to the ring-osc clock. note, however, that the following peripheral hardware can be used when the cpu operates on the ring-osc clock. ? ? ? ? watchdog timer ? ? ? ? clock monitor ? ? ? ? 8-bit timer h1 when f r /2 7 is selected as count clock ? ? ? ? peripheral hardware selecting external clock as the clock source (except when external count clock of tm0n (n = 0, 1) is selected (ti00n valid edge)) 2. set mcs = 1 and mcm0 = 1 before switching subsystem clock operation to x1 input clock operation (bit 4 (css) of the processor clock control register (pcc) is changed from 1 to 0).
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 139 (4) main osc control register (moc) this register selects the operation mode of the x1 input clock. this register is used to stop the x1 oscillator operation when the cpu is operating with the ring-osc clock. therefore, this register is valid only when the cpu is operating with the ring-osc clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 6-6. format of main osc control register (moc) address : ffa2h after reset : 00h r/w symbol 76543210 mocmstop0000000 mstop control of x1 oscillator operation 0 x1 oscillator operating 1 x1 oscillator stopped cautions 1. make sure that bit 1 (mcs) of the main clock mode register (mcm) is 0 before setting mstop. 2. to stop x1 oscillation during operation with the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc) to 1 (setting by mstop is not possible). (5) oscillation stabilization time counter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. reset input, stop instruction, mstop = 1, and mcc = 1 clear ostc to 00h. figure 6-7. format of oscillation stabilization time counter status register (ostc) address : ffa3h after reset : 00h r symbol 76543210 ostc 0 0 0 most11 most13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 10000 2 11 /f xp min. (204.8 s min.) 11000 2 13 /f xp min. (819.2 s min.) 111002 14 /f xp min. (1.64 ms min.) 111102 15 /f xp min. (3.27 ms min.) 111112 16 /f xp min. (6.55 ms min.) caution after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 6 clock generator preliminary user?s manual u15947ej1v1ud 140 (6) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabilization wait time when stop mode is released. the wait time set by osts is valid only after stop mode is released with the x1 input clock selected as cpu clock. after stop mode is released with ring-osc selected as cpu clock, the oscillation stabilization time must be confirmed by ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 6-8. format of oscillation stabilization time select register (osts) address : ffa4h after reset : 05h r/w symbol 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 001 2 11 /f xp (204.8 s) 010 2 13 /f xp (819.2 s) 0112 14 /f xp (1.64 ms) 1002 15 /f xp (3.27 ms) 1012 16 /f xp (6.55 ms) other than above setting prohibited cautions 1. if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? ? ? ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 2. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. stop mode release x1 pin voltage waveform v ss a remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 141 6.4 system clock oscillator 6.4.1 x1 oscillator the x1 oscillator oscillates with a crystal resonator or ceramic resonator (standard: 8.38 mhz, 10 mhz when regc pin is directly connected to v dd ) connected to the x1 and x2 pins. an external clock can be input to the x1 oscillator when the regc pin is directly connected to v dd . in this case, input the clock signal to the x1 pin and input the inverse signal to the x2 pin. figure 6-9 shows the external circuit of the x1 oscillator. figure 6-9. external circuit of x1 oscillator (a) crystal, ceramic oscillation (b) external clock ic x1 x2 crystal resonator or ceramic resonator v ss external clock x1 x2 6.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator when the regc pin is directly connected to v dd . in this case, input the clock signal to the xt1 pin and the inverse signal to the xt2 pin. figure 6-10 shows an external circuit of the subsystem clock oscillator. figure 6-10. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 ic xt1 32.768 khz xt1 xt2 pd74hcu04 external clock v ss cautions are listed on the next page.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 142 cautions 1. when using the x1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the figure 6-11 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption. figure 6-11 shows examples of incorrect resonator connection. figure 6-11. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line x1 ic x2 x2 ic x1 port v ss v ss remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 143 figure 6-11. examples of incorrect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ic x2 x1 ic x2 x1 ab c pmn v dd0 high current high current v ss v ss (e) signals are fetched ic x2 x1 v ss remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire x2 and xt1 so that they are not in parallel, and to connect the ic pin between x2 and xt1 directly to v ss .
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 144 6.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect to ev dd or v dd xt2: leave open in this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the x1 input clock and ring-osc clock stop. to minimize leakage current, the above on-chip feedback resistor can be set not to be used via bit 6 (frc) of the processor clock control register (pcc). in this case also, connect the xt1 and xt2 pins as described above. 6.4.4 ring-osc oscillator ring-osc oscillator is incorporated in the pd780143, 780144, 780146, 780148, and 78f0148. ? can be stopped by software ? or ? cannot be stopped ? can be selected by a mask option. the ring-osc clock always oscillates after reset release (240 khz (typ.)). 6.4.5 prescaler the prescaler generates various clocks by dividing the x1 oscillator output (f x ) when the x1 input clock is selected as the clock to be supplied to the cpu. caution when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing the ring-osc oscillator output (f x ) (f x = 240 khz (typ.)). 6.5 clock generator operation the clock generator generates the following clocks and controls the operation modes of the cpu, such as standby mode. ? x1 input clock f xp ? ring-osc clock f r ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the cpu starts operation when the on-chip ring-osc oscillator starts outputting after reset release in the 78k0/kf1 series, thus enabling the following. (1) enhancement of security function when the x1 input clock is set as the cpu clock by the default setting, the device cannot operate if the x1 input clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the on-chip ring-osc clock, so the device can be started by the ring-osc clock after reset release by the clock monitor (detection of x1 input clock stop). consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 145 (2) improvement of performance because the cpu can be started without waiting for the x1 input clock oscillation stabilization time, the total performance can be improved. a timing diagram of the cpu default start using ring-osc is shown in figure 6-12. figure 6-12. timing diagram of cpu default start using ring-osc ring-osc clock (f r ) cpu clock x1 input clock (f xp ) operation stopped: 17/f r x1 oscillation stabilization time: 2 11 /f xp to 2 16 /f xp note reset ring-osc clock x1 input clock switched by software subsystem clock (f xt ) note check using the oscillation stabilization time counter status register (ostc). (a) when the reset signal is generated, bit 0 of the main clock mode register (mcm) is set to 0 and the ring- osc clock is set as the cpu clock. however, a clock is supplied to the cpu after 17 clocks of the ring-osc clock have elapsed after reset release (or clock supply to the cpu stops for 17 clocks). during the reset period, oscillation of the x1 input clock and ring-osc clock is stopped. (b) after reset release, the cpu clock can be switched from the ring-osc clock to the x1 input clock using bit 0 (mcm0) of the main clock mode register (mcm) after the x1 input clock oscillation stabilization time has elapsed. at this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (ostc) before switching the cpu clock. the cpu clock status can be checked using bit 1 (mcs) of mcm. (c) ring-osc can be set to stopped/oscillating using the ring-osc mode register (rcm) when ? can be stopped by software ? is selected for the ring-osc by a mask option, if the x1 input or subsystem clock is used as the cpu clock. make sure that mcs is 1 at this time. (d) when ring-osc is used as the cpu clock, the x1 input clock can be set to stopped/oscillating using the main osc control register (moc). make sure that mcs is 0 at this time. when the subsystem clock is used as the cpu clock, whether the x1 input clock stops or oscillates can be set by the processor clock control register (pcc). in addition, halt mode can be used during operation with the subsystem clock, but stop mode cannot be used (subsystem clock oscillation cannot be stopped by the stop instruction).
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 146 (e) select the x1 input clock oscillation stabilization time (2 11 /f xp , 2 13 /f xp , 2 14 /f xp , 2 15 /f xp , 2 16 /f xp ) using the oscillation stabilization time select register (osts) when releasing stop mode while x1 input clock is being used as the cpu clock. in addition, when releasing stop mode while reset is released and ring-osc clock is being used as the cpu clock, check the x1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc). a status transition diagram of this product is shown in figure 6-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in tables 6-3 and 6-4, respectively. figure 6-13. status transition diagram (1/4) (1) when ? ring-osc can be stopped by software ? is selected by mask option (when subsystem clock is not used) status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt reset release interrupt interrupt halt instruction stop instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction halt instruction stop note 4 reset note 5 notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 3. when shifting from status 2 to status 1, make sure that mcs is 0. 4. when ? ring-osc can be stopped by software ? is selected by a mask option, the watchdog timer stops operating in the halt and stop modes, regardless of the source clock of the watchdog timer. however, oscillation of ring-osc does not stop even in the halt and stop modes if rstop = 0. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 147 figure 6-13. status transition diagram (2/4) (2) when ? ring-osc can be stopped by software ? is selected by mask option (when subsystem clock is used) halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt interrupt halt instruction halt instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcc = 0 css = 0 note 6 mcc = 1 css = 1 note 5 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction stop note 4 reset note 7 status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating reset release interrupt halt instruction status 6 cpu clock: f xt f xp : oscillation stopped f r : oscillating/ oscillation stopped status 5 cpu clock: f xt f xp : oscillating f r : oscillating/ oscillation stopped notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 3. when shifting from status 2 to status 1, make sure that mcs is 0. 4. when ? ring-osc can be stopped by software ? is selected by a mask option, the ring-osc oscillator is stopped after the halt or stop instruction has been executed, regardless of the setting of bit 0 (rstop) of the ring-osc mode register (rcm) and bit 0 (mcm0) of the main clock mode register (mcm). 5. shifting to status 5 (subsystem clock operation) can be performed only from status 3 or 4 (x1 input clock operation). 6. shifting to status 1 or status 2 from status 5 is not possible. 7. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 148 figure 6-13. status transition diagram (3/4) (3) when ? ring-osc cannot be stopped ? is selected by mask option (when subsystem clock is not used) status 3 cpu clock: f xp f xp : oscillating f r : oscillating halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 4 status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 2. when shifting from status 2 to status 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ? ring-osc cannot be stopped ? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using the tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an internal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 149 figure 6-13. status transition diagram (4/4) (4) when ? ring-osc cannot be stopped ? is selected by mask option (when subsystem clock is used) halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 6 interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release mcc = 0 css = 0 note 5 mcc = 1 css = 1 note 4 interrupt interrupt halt instruction halt instruction status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 5 cpu clock: f xt f xp : oscillation stopped f r : oscillating/ oscillation stopped status 4 cpu clock: f xt f xp : oscillating f r : oscillating/ oscillation stopped notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 2. when shifting from status 2 to status 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ? ring-osc cannot be stopped ? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using the tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an internal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. shifting to status 4 (subsystem clock operation) can be performed only from status 3 (x1 input clock operation). 5. shifting to status 1 or status 2 from status 4 is not possible. 6. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 150 table 6-3. relationship between operation clocks in each operation status ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode x1 oscillator note 1 rstop = 0 rstop = 1 subsystem clock oscillator cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped stopped ring-osc stopped stop stopped note 3 stopped halt oscillating oscillating oscillating stopped oscillating note 4 ring-osc x1 caution the rstop setting is valid only when ? can be stopped by software ? is set for ring-osc by a mask option. notes 1. when ? cannot be stopped ? is selected for ring-osc by a mask option. 2. when ? can be stopped by software ? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. remark rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) table 6-4. oscillation control flags and clock oscillation status x1 oscillator ring-osc oscillator rstop = 0 stopped oscillating mstop = 1 note rstop = 1 setting prohibited rstop = 0 oscillating mstop = 0 note rstop = 1 oscillating stopped rstop = 0 oscillating mcc = 1 note rstop = 1 stopped stopped rstop = 0 oscillating mcc = 0 note rstop = 1 oscillating stopped note setting x1 oscillator oscillating/stopped differs depending on the cpu clock used. ? when the ring-osc clock is used as the cpu clock: set using the mstop bit ? when the subsystem clock is used as the cpu clock: set using the mcc bit caution the rstop setting is valid only when ? can be stopped by software ? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm)
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 151 6.6 time required to switch between ring-osc clock and x1 input clock bit 0 (mcm0) of the main clock mode register (mcm) is used to switch between the ring-osc clock and x1 input clock. in the actual switching operation, switching does not occur immediately after mcm0 rewrite; several instructions are executed using the pre-switch clock after switching mcm0 (see table 6-5 ). bit 1 (mcs) of mcm is used to judge that operation is performed using either the ring-osc clock or x1 input clock. to stop the clock, wait for the number of clocks shown in table 6-5 before stopping. table 6-5. time required to switch between ring-osc clock and x1 input clock pcc time required for switching pcc2 pcc1 pcc0 x1 ring-osc ring-osc x1 000f xp /f r + 1 clock 001f xp /2f r + 1 clock 010f xp /4f r + 1 clock 011f xp /8f r + 1 clock 100f xp /16f r + 1 clock 2 clocks caution to calculate the maximum time, set f r = 120 khz. remarks 1. pcc: processor clock control register 2. f xp : x1 input clock oscillation frequency 3. f r : ring-osc clock oscillation frequency 4. the maximum time is the number of clocks of the cpu clock before switching.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 152 6.7 changing system clock and cpu clock settings 6.7.1 time required for switching between system clock and cpu clock the system clock and cpu clock can be switched using bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed immediately after rewriting to the pcc; operation continues on the pre-switchover clock for several instructions (see table 6-6 ). whether the system is operating on the x1 input clock (or ring-osc clock) or the subsystem clock can be ascertained using bit 5 (cls) of the pcc register. table 6-6. maximum time required for cpu clock switchover set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 000000010010001101001 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks f xp /f xt clocks (306 clocks) 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /2f xt clocks (153 clocks) 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /4f xt clocks (77 clocks) 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /8f xt clocks (39 clocks) 0 1 0 0 1 clock 1 clock 1 clock 1 clock f xp /16f xt clocks (20 clocks) 1 1 clock 1 clock 1 clock 1 clock 1 clock remarks 1. the maximum time is the number of clocks of the cpu clock before switching. 2. figures in parentheses apply to operation with f xp = 10 mhz and f xt = 32.768 khz. caution selection of the cpu clock cycle division factor (pcc0 to pcc2) and switchover from the x1 input clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle division factor (pcc0 to pcc2) and switchover from the subsystem clock to the x1 input clock (changing css from 1 to 0).
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 153 6.8 clock switching flowchart and register setting 6.8.1 switching from ring-osc clock to x1 input clock figure 6-14. switching from ring-osc clock to x1 input clock ; f cpu = f r ; ring-osc oscillation ; ring-osc clock operation ; x1 oscillation ; oscillation stabilization time status register ; oscillation stabilization time f xp /2 16 mcm.1 (mcs) is changed from 0 to 1 ; x1 oscillation stabilization time status check x1 oscillation stabilization time has elapsed x1 oscillation stabilization time has not elapsed pcc = 00h rcm = 00h mcm = 00h moc = 00h ostc = 00h osts = 05h note ostc check note each processing after reset release pcc setting mcm.0 1 x1 input clock operation ring-osc clock operation (dividing set pcc) register initial value after reset ring-osc clock operation x1 input clock operation note check the oscillation stabilization wait time of the x1 oscillator after reset release using the ostc register and then switch to the x1 input clock operation after the oscillation stabilization wait time has elapsed. the osts register setting is valid only after stop mode is released during x1 input clock operation.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 154 6.8.2 switching from x1 input clock to ring-osc clock figure 6-15. switching from x1 input clock to ring-osc clock (flowchart) mcm.1 (mcs) is changed from 1 to 0 ; ring-osc clock operation ; ring-osc oscillating? ring-osc clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation no: rstop = 0 yes: rstop = 1 pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h rcm.0 note (rstop) = 1? rstop = 0 mcm0 0 register setting in x1 input clock operation x1 input clock operation ring-osc clock operation note required only when ? clock can be stopped by software ? is selected for ring-osc by a mask option.
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 155 6.8.3 switching from x1 input clock to subsystem clock figure 6-16. switching from x1 input clock to subsystem clock (flowchart) mcs = 1 not changed. cls is changed from 0 to 1. ; subsystem clock operation subsystem clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h css 1 register setting in x1 input clock operation x1 input clock operation subsystem clock
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 156 6.8.4 switching from subsystem clock to x1 input clock figure 6-17. switching from subsystem clock to x1 input clock (flowchart) ; subsystem clock operation ; x1 oscillating? ; x1 oscillation enabled ; wait for x1 oscillation stabilization time ; x1 input clock operation cls is changed from 1 to 0. mcs = 1 not changed. x1 oscillation stabilization time elapsed x1 oscillation stabilization time not elapsed yes: x1 oscillation stopped no: x1 oscillating mcc 0 pcc.4 (css) = 1 mcm = 03h mcc = 1? ostc check css 0 x1 input clock operation subsystem clock operation x1 input clock operation
chapter 6 clock generator preliminary user ? s manual u15947ej1v1ud 157 6.8.5 register settings table 6-7. clock and register setting setting flag status flag pcc register mcm register moc register rcm register pcc register mcm register f cpu mode mcc css mcm0 mstop rstop note 1 cls mcs ring-osc oscillating 0010001 x1 input clock note 2 ring-osc stopped 0010101 x1 oscillating 0000000 ring-osc clock x1 stopped 0 note 3 001000 x1 oscillating, ring-osc oscillating 0 1 1 note 5 0 note 6 011 x1 stopped, ring-osc oscillating 1 1 1 note 5 0 note 6 011 x1 oscillating, ring-osc stopped 0 1 1 note 5 0 note 6 111 subsystem clock note 4 x1 stopped, ring-osc stopped 1 1 1 note 5 0 note 6 111 notes 1. valid only when ? clock can be stopped by software ? is selected for ring-osc by a mask option. 2. do not set mcc = 1 or mstop = 1 during x1 input clock operation (even if mcc = 1 or mstop = 1 is set, the x1 oscillation does not stop). 3. do not set mcc = 1 during ring-osc operation (even if mcc = 1 is set, the x1 oscillation does not stop). to stop x1 oscillation during ring-osc operation, use mstop. 4. shifting to subsystem clock operation mode must be performed from the x1 input clock operation mode. from subsystem clock operation mode, only x1 input clock operation mode can be shifted to. 5. do not set mcm0 = 0 (shifting to ring-osc) during subsystem clock operation. 6. do not set mstop = 1 during subsystem clock operation (even if mstop = 1 is set, x1 oscillation does not stop). to stop x1 oscillation during subsystem clock operation, use mcc.
preliminary user?s manual u15947ej1v1ud 158 chapter 7 16-bit timer/event counters 00 and 01 the pd780143 and 780144 incorporate 16-bit timer/event counter 00, and the pd780146, 780148, and 78f0148 incorporate 16-bit timer/event counters 00 and 01. 7.1 functions of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 note have the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output (1) interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) ppg output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. (4) external event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (5) square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (6) one-shot pulse output 16-bit timer/event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. note available only for the pd780146, 780148, and 78f0148.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u15947ej1v1ud 159 7.2 configuration of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 consist of the following hardware. table 7-1. configuration of 16-bit timer/event counters 00 and 01 item configuration timer counter 16 bits 1 (tm0n) register 16-bit timer capture/compare register: 16 bits 2 (cr00n, cr01n) timer output 1 (to0n) control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0 (pm0) note note see figure 4-2 block diagram of p00, p03, and p05 and figure 4-3 block diagram of p01 and p06 . remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 figures 7-1 and 7-2 show the block diagrams. figure 7-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f x f x /2 2 f x /2 8 f x ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 160 figure 7-2. block diagram of 16-bit timer/event counter 01 internal bus capture/compare control register 01 (crc01) ti011/to01/p06 f x f x /2 4 f x /2 6 f x ti001/p05 prescaler mode register 01 (prm01) 2 prm011 prm010 crc012 16-bit timer capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) clear noise elimi- nator crc012 crc011 crc010 inttm001 to01/ti011/ p06 inttm011 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 toc014 lvs01 lvr01 toc011 toe01 selector 16-bit timer capture/compare register 001 (cr001) selector selector selector noise elimi- nator noise elimi- nator output controller ospe01 ospt01
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 161 (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of ti00n is input in the mode in which clear & start occurs when inputting the valid edge of ti00n <4> if tm0n and cr00n match in the mode in which clear & start occurs on a match of tm0n and cr00n <5> ospt0n is set in one-shot pulse output mode (2) 16-bit timer capture/compare register 00n (cr00n) cr00n is a 16-bit register that has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc0n0) of capture/compare control register 0n (crc0n). ? ? ? ? when cr00n is used as a compare register the value set in cr00n is constantly compared with the 16-bit timer counter 0n (tm0n) count value, and an interrupt request (inttm00n) is generated if they match. it can also be used as the register that holds the interval time when tm0n is set to interval timer operation. ? ? ? ? when cr00n is used as a capture register it is possible to select the valid edge of the ti00n pin or the ti01n pin as the capture trigger. the ti00n or ti01n valid edge is set using prescaler mode register 0n (prm0n). if the capture trigger is specified to be the valid edge of the ti00n pin, the situation is as shown in table 7-2. on the other hand, when the capture trigger is specified to be the valid edge of the ti01n pin, the situation is as shown in table 7-3. table 7-2. ti00n pin valid edge and cr00n, cr01n capture trigger es0n1 es0n0 ti00n pin valid edge cr00n capture trigger cr01n capture trigger 0 0 falling edge rising edge falling edge 0 1 rising edge falling edge rising edge 1 0 setting prohibited setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation both rising and falling edges table 7-3. ti01n pin valid edge and cr00n capture trigger es1n1 es1n0 ti01n pin valid edge cr00n capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u15947ej1v1ud 162 cr00n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. cautions 1. set a value other than 0000h in cr00n in the mode in which clear & start occurs on a match of tm0n and cr00n. however, in the free-running mode and in the clear mode using the valid edge of ti00n, if cr00n is set to 0000h, an interrupt request (inttm00n) is generated following overflow (ffffh). 2. if the changed value of cr00n is smaller than the value of 16-bit timer counter 0n (tm0n), tm0n continues counting and starts counting again from 0 after overflow. therefore, if the value of cr00n after the change is smaller than before the change, the timer should be restarted after cr00n is changed. 3. when p01 or p06 is used as the valid edge of ti01n, it cannot be used as the timer output (to0n). moreover, when p01 or p06 is used as to0n, it cannot be used as the valid edge of ti01n. 4. when cr00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. 5. do not rewrite cr00n during tm0n operation. (3) 16-bit timer capture/compare register 01n (cr01n) cr01n is a 16-bit register that has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc0n2) of capture/compare control register 0n (crc0n). ? ? ? ? when cr01n is used as a compare register the value set in the cr01n is constantly compared with the 16-bit timer counter 0n (tm0n) count value, and an interrupt request (inttm01n) is generated if they match. ? ? ? ? when cr01n is used as a capture register it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n valid edge is set by prescaler mode register 0n (prm0n). cr01n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 cautions 1. set cr01n to other than 0000h. this means a 1-pulse count operation cannot be performed when cr01n is used as the event counter. however, in the free-running mode and in the clear mode using the valid edge of ti00n, if cr01n is set to 0000h, an interrupt request (inttm01n) is generated following overflow (ffffh). 2. when cr01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. 3. cr01n can be rewritten during tm0n operation. for details, refer to remark 2 in figure 7- 17.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 163 7.3 registers controlling 16-bit timer/event counters 00 and 01 the following five registers are used to control 16-bit timer/event counters 00 and 01. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare control register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? port mode register 0 (pm0) (1) 16-bit timer mode control register 0n (tmc0n) this register sets the 16-bit timer operating mode, the 16-bit timer counter 0n (tm0n) clear mode, and output timing, and detects an overflow. tmc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0n to 00h. caution 16-bit timer counter 0n (tm0n) starts operation at the moment tmc0n2 and tmc0n3 are set to values other than 0, 0 (operation stop mode), respectively. set tmc0n2 and tmc0n3 to 0, 0 to stop the operation. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 164 figure 7-3. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 0 ovf00 symbol tmc00 address ffbah after reset: 00h r/w tmc003 tmc002 tmc001 operating mode and clear mode selection to00 output timing selection interrupt request generation 000 001 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 011 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 100 101 clear & start occurs on ti000 valid edge ? 1 1 0 clear & start occurs on match between tm00 and cr000 match between tm00 and cr000 or match between tm00 and cr010 1 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge generated on match between tm00 and cr000, or match between tm00 and cr010 ovf00 16-bit timer counter 00 (tm00) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf00 flag. 2. set the valid edge of the ti000/p00 pin using prescaler mode register 00 (prm00). 3. if any the following modes: the mode in which clear & start occurs on match between tm00 and cr000, the mode in which clear & start occurs at the ti00 valid edge, or free-running mode is selected, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remarks 1. to00: 16-bit timer/event counter 00 output pin 2. ti000: 16-bit timer/event counter 00 input pin 3. tm00: 16-bit timer counter 00 4. cr000: 16-bit timer capture/compare register 000 5. cr010: 16-bit timer capture/compare register 010
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 165 figure 7-4. format of 16-bit timer mode control register 01 (tmc01) 7 0 6 0 5 0 4 0 3 tmc013 2 tmc012 1 tmc011 0 ovf01 symbol tmc01 address ffb6h after reset: 00h r/w tmc013 tmc012 tmc011 operating mode and clear mode selection to01 output timing selection interrupt request generation 000 001 operation stop (tm01 cleared to 0) no change not generated 0 1 0 free-running mode match between tm01 and cr001 or match between tm01 and cr011 011 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge 100 101 clear & start occurs on ti001 valid edge ? 1 1 0 clear & start occurs on match between tm01 and cr001 match between tm01 and cr001 or match between tm01 and cr011 1 1 1 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge generated on match between tm01 and cr001, or match between tm01 and cr011 ovf01 16-bit timer counter 01 (tm01) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf01 flag. 2. set the valid edge of the ti001/p05 pin using prescaler mode register 01 (prm01). 3. if any the following modes: the mode in which clear & start occurs on match between tm01 and cr001, the mode in which clear & start occurs at the ti01 valid edge, or free-running mode is selected, when the set value of cr001 is ffffh and the tm01 value changes from ffffh to 0000h, the ovf01 flag is set to 1. remarks 1. to01: 16-bit timer/event counter 01 output pin 2. ti001: 16-bit timer/event counter 01 input pin 3. tm01: 16-bit timer counter 01 4. cr001: 16-bit timer capture/compare register 001 5. cr011: 16-bit timer capture/compare register 011
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 166 (2) capture/compare control register 0n (crc0n) this register controls the operation of the 16-bit timer capture/compare registers (cr00n, cr01n). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0n to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 figure 7-5. format of capture/compare control register 00 (crc00) address: ffbch after reset: 00h r/w symbol76543210 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 1 captures on valid edge of ti000 by reverse phase crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc00. 2. when the mode in which clear & start occurs on a match between tm00 and cr000 is selected with 16-bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. 3. to ensure that the capture operation is performed properly, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (prm00).
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 167 figure 7-6. format of capture/compare control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol76543210 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 1 captures on valid edge of ti001 by reverse phase crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc01. 2. when the mode in which clear & start occurs on a match between tm01 and cr001 is selected with 16-bit timer mode control register 01 (tmc01), cr001 should not be specified as a capture register. 3. to ensure that the capture operation is performed properly, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 01 (prm01). (3) 16-bit timer output control register 0n (toc0n) this register controls the operation of the 16-bit timer/event counter 0n output controller. it sets/resets the r-s type flip-flop (lv0n), enables/disables output inversion and 16-bit timer/event counter 0n timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0n to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 168 figure 7-7. format of 16-bit timer output control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol76543210 toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 16-bit timer/event counter 00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 16-bit timer/event counter 00 output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 valid edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possible because an overflow does not occur. cautions 1. timer operation must be stopped before setting other than toc004. 2. if lvs00 and lvr00 are read after data is set, 0 is read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of the operating clock is required to write to ospt00 successively.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 169 figure 7-8. format of 16-bit timer output control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol76543210 toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe01 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc014 timer output f/f control using match of cr011 and tm01 0 disables inversion operation 1 enables inversion operation lvs01 lvr01 16-bit timer/event counter 01 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc011 timer output f/f control using match of cr001 and tm01 0 disables inversion operation 1 enables inversion operation toe01 16-bit timer/event counter 01 output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the ti001 valid edge. in the mode in which clear & start occurs on a match between the tm01 register and cr001 register, one-shot pulse output is not possible because an overflow does not occur. cautions 1. timer operation must be stopped before setting other than toc014. 2. if lvs01 and lvr01 are read after data is set, 0 is read. 3. ospt01 is automatically cleared after data is set, so 0 is read. 4. do not set ospt01 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of the operating clock is required to write to ospt01 successively.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 170 (4) prescaler mode register 0n (prm0n) this register is used to set the 16-bit timer counter 0n (tm0n) count clock and ti00n and ti01n input valid edges. prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears prm0n to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 171 figure 7-9. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol76543210 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 00f x (10 mhz) 01f x /2 2 (2.5 mhz) 10f x /2 8 (39.06 khz) 1 1 ti000 valid edge note note the external clock requires a pulse two times longer than internal clock (f x ). cautions 1. if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti000 and the capture trigger. 2. always set data to prm00 after stopping the timer operation. 3. if the ti000 or ti010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (tm00). care is therefore required when pulling up the ti000 or ti010 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. 4. when p01 is used as the ti010 valid edge, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge. remarks 1 .f x : x1 input clock oscillation frequency 2. ti000, ti010: 16-bit timer/event counter 00 input pin 3. figures in parentheses are for operation with f x = 10 mhz.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user?s manual u15947ej1v1ud 172 figure 7-10. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol76543210 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm011 prm010 count clock selection 00f x (10 mhz) 01f x /2 4 (625 khz) 10f x /2 6 (156.25 khz) 1 1 ti001 valid edge note note the external clock requires a pulse two times longer than internal clock (f x ). cautions 1. if the valid edge of ti001 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti001 and the capture trigger. 2. always set data to prm01 after stopping the timer operation. 3. if the ti001 or ti011 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti001 pin or ti011 pin to enable the operation of 16-bit timer counter 01 (tm01). care is therefore required when pulling up the ti001 or ti011 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. 4. when p06 is used as the ti011 valid edge, it cannot be used as the timer output (to01), and when used as to01, it cannot be used as the ti011 valid edge. remarks 1 .f x : x1 input clock oscillation frequency 2. ti001, ti011: 16-bit timer/event counter 01 input pin 3. figures in parentheses are for operation with f x = 10 mhz.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 173 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 and p06/to01 note /ti011 note pins for timer output, set pm01 and pm06 and the output latch of p01 and p06 to 0. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 7-11. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) note available only for the pd780146, 780148, and 78f0148.
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 174 7.4 operation of 16-bit timer/event counters 00 and 01 7.4.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-12 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (cr00n) as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set in cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of the 16-bit timer/event counter 0n can be selected with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). see 7.5 cautions for 16-bit timer/event counters 00 and 01 (2) 16-bit timer capture/compare register setting for details of the operation when the compare register value is changed during timer count operation. figure 7-12. control register settings for interval timer operation (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare control register 0n (crc0n) 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. for details, see figures 7-3 to 7-6 . 2. n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 175 figure 7-13. interval timer configuration diagram 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) ovf0n clear circuit inttm00n f x (f x ) f x /2 2 (f x /2 4 ) f x /2 8 (f x /2 6 ) ti000/p00 (ti001/p05) selector noise eliminator f x remark frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 7-14. timing of interval timer operation count clock t tm0n count value cr00n inttm00n to0n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n count start clear clear interrupt acknowledged interrupt acknowledged interval time interval time interval time remark interval time = (n + 1) t n = 0001h to ffffh n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 176 7.4.2 ppg output operations setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-15 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, rectangular waves are output from the to0n pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 01n (cr01n) and in 16-bit timer capture/compare register 00n (cr00n), respectively. figure 7-15. control register settings for ppg output operation (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare control register 0n (crc0n) 00000 crc0n2 0 crc0n1 crc0n0 0 crc0n cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 ospt0n 0 ospe0n 0 toc0n4 1 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output inverts output on match between tm0n and cr00n specifies initial value of to0n output f/f inverts output on match between tm0n and cr01n disables one-shot pulse output cautions 1. values in the following range should be set in cr00n and cr01n: 0000h < cr01n < cr00n ffffh 2. the cycle of the pulse generated through ppg output (cr00n setting value + 1) has a duty of (cr01n setting value + 1)/(cr00n setting value + 1). remark : don ? t care n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 177 figure 7-16. configuration of ppg output 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) clear circuit noise eliminator f x f x (f x ) f x /2 2 (f x /2 4 ) f x /2 8 (f x /2 6 ) ti000/p00 (ti001/p05) 16-bit timer capture/compare register 01n (cr01n) to00/ti010/p01 ( to01/ti011/p06 ) selector output controller remark frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 7-17. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm0n count value to0n pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00n capture value cr01n capture value m m n ? 1 n clear count start caution cr00n cannot be rewritten during tm0n operation. remarks 1. 0000h < m < n ffffh 2. in the ppg output operation, change the pulse width (rewrite cr01n) during tm0n operation using the following procedure. <1> disable the timer output inversion operation by match of tm0n and cr01n (toc0n4 = 0) <2> disable the inttm01n interrupt (tmmk01n = 1) <3> rewrite cr01n <4> wait for 1 cycle of the tm0n count clock <5> enable the timer output inversion operation by match of tm0n and cr01n (toc0n4 = 1) <6> clear the interrupt request flag of inttm01n (tmif01n = 0) <7> enable the inttm01n interrupt (tmmk01n = 0) 3. n = 0: pd780143, 780144, n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 178 7.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00n pin and ti01n pin using 16-bit timer counter 0n (tm0n). there are two measurement methods: measuring with tm0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00n pin. (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see register settings in figure 7-18 ), and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. any of three edges ? rising, falling, or both edges ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prm0n. for valid edge detection, sampling is performed using the count clock selected by prm0n, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 7-18. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare control register 0n (crc0n) 00000 crc0n2 1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register cr01n used as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 7-3 to 7-6 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 179 figure 7-19. configuration diagram for pulse width measurement with free-running counter f x (f x ) f x /2 2 (f x /2 4 ) f x /2 8 (f x /2 6 ) ti00n 16-bit timer counter 0n (tm0n) ovf0n 16-bit timer capture/compare register 01n (cr01n) internal bus inttm01n selector remark frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 7-20. timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0n count value ti00n pin input cr01n capture value inttm01n ovf0n (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 180 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see figure 7-21 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n pin and the ti01n pin. when the edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es1n0 and es1n1) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n) and an interrupt request signal (inttm00n) is set. any of three edges ? rising, falling, or both edges ? can be selected as the valid edge of the ti00n pin and the ti01n pin, specified using bits 4 and 5 (es0n0 and es0n1) and bits 6 and 7 (es1n0 and es1n1) of prm0n, respectively. for valid edge detection of the ti00n and ti01n pins, sampling is performed at the interval selected by prescaler mode register 0n (prm0n), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 7-21. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare control register 0n (crc0n) 00000 crc0n2 1 crc0n1 0 crc0n0 1 crc0n cr00n used as capture register captures valid edge of ti01n pin to cr00n cr01n used as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figures 7-3 and 7-4 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 181 ? ? ? ? capture operation (free-running mode) the capture register operation when capture trigger is input is shown below. figure 7-22. cr01n capture operation with rising edge specified count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n+1 n figure 7-23. timing of pulse width measurement operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01n pin input cr00n capture value inttm01n inttm00n ovf0n (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 count clock tm0n count value ti00n pin input cr01n capture value remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 182 (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see figure 7-24 ), it is possible to measure the pulse width of the signal input to the ti00n pin. when the edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation is input into cr01n, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n). either of two edges ? rising or falling ? can be selected as the valid edge of the ti00n pin specified using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). for ti00n pin valid edge detection, sampling is performed at the interval selected by prescaler mode register 0n (prm0n), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 7-24. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare control register 0n (crc0n) 00000 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 183 figure 7-25. timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm01n ovf0n d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (4) pulse width measurement by means of restart when input of a valid edge to the ti00n pin is detected, the count value of 16-bit timer counter 0n (tm0n) is taken into 16-bit timer capture/compare register 01n (cr01n), and then the pulse width of the signal input to the ti00n pin is measured by clearing tm0n and restarting the count operation (see figure 7-26 ). either of two edges ? rising or falling ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). in valid edge detection, sampling is performed using the count clock cycle selected by prescaler mode register 0n (prm0n) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 184 figure 7-26. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 0 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. (b) capture/compare control register 0n (crc0n) 00000 crc0n2 1 crc0n1 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figures 7-3 and 7-4 . figure 7-27. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01n d1 t d2 t d2 d1 d2 d1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 185 7.4.4 external event counter operation the external event counter counts the number of external clock pulses input to the ti00n pin using 16-bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit timer capture/compare register 00n (cr00n) value, tm0n is cleared to 0 and the interrupt request signal (inttm00n) is generated. input a value other than 0000h to cr00n (a count operation with 1-bit pulse cannot be carried out). any of three edges ? rising, falling, or both edges ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). because operation is carried out only after the valid edge is detected twice by sampling using the internal clock (f x ), noise with short pulse widths can be eliminated. figure 7-28. control register settings in external event counter mode (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare control register 0n (crc0n) 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. for details, see figures 7-3 to 7-6 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 186 figure 7-29. configuration diagram of external event counter 16-bit timer capture/compare register 00n (cr00n) internal bus match clear ovf0n inttm00n f x /2 2 (f x /2 4 ) f x /2 8 (f x /2 6 ) f x (f x ) noise eliminator f x valid edge of ti00n 16-bit timer/counter 0n (tm0n) 16-bit timer capture/compare register 01n (cr01n) selector noise eliminator remark frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 7-30. external event counter operation timing (with rising edge specified) ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm0n should be read. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 187 7.4.5 square-wave output operation a square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer capture/compare register 00n (cr00n). the to0n pin output status is reversed at intervals of the count value preset to cr00n by setting bit 0 (toe0n) and bit 1 (toc0n1) of 16-bit timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. figure 7-31. control register settings in square-wave output mode (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare control register 0n (crc0n) 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 ospt0n 0 ospe0n 0 toc0n4 0 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f. does not invert output on match between tm0n and cr01n. disables one-shot pulse output. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. for details, see figures 7-5 to 7-8 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 188 figure 7-32. square-wave output operation timing count clock tm0n count value cr00n inttm00n to0n pin output 0000h 0001h 0002h n ? 1n 0000h 0001h 0002h n ? 1n 0000h n 7.4.6 one-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti00n pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-33, and by setting bit 6 (ospt0n) of the toc0n register to 1 by software. by setting the ospt0n bit to 1, 16-bit timer/event counter 0n is cleared and started, and its output becomes active at the count value (n) set in advance to 16-bit timer capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 00n (cr00n) note . even after the one-shot pulse has been output, the tm0n register continues its operation. to stop the tm0n register, the tmc0n3 and tmc0n2 bits of the tmc0n register must be set to 00. note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. cautions 1. do not set the ospt0n bit while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the ti00n pin or its alternate-function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 189 figure 7-33. control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control register 0n (tmc0n) 00000 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running mode 100 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr00n as compare register cr01n as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 0 1 1 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output inverts output upon match between tm0n and cr00n specifies initial value of to0n output f/f inverts output upon match between tm0n and cr01n sets one-shot pulse output mode set to 1 for output 0/1 1 1 caution do not set 0000h to the cr00n and cr01n registers. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figures 7-5 to 7-8 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 190 figure 7-34. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm0n count cr01n set value cr00n set value ospt0n inttm01n inttm00n to0n pin output set tmc0n to 0ch (tm0n count starts) caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc0n3 and tmc0n2 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-35, and by using the valid edge of the ti00n pin as an external trigger. the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00n pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (cr00n) note . note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. caution even if the external trigger is generated again while the one-shot pulse is output, it is ignored. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 191 figure 7-35. control register settings for one-shot pulse output with external trigger (a) 16-bit timer mode control register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti00n pin 000 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 00 1 1 0/1 toc0n lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n enables to0n output inverts output upon match between tm0n and cr00n specifies initial value of to0n output f/f inverts output upon match between tm0n and cr01n sets one-shot pulse output mode 0/1 1 1 caution do not set 0000h to the cr00n and cr01n registers. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figures 7-5 to 7-8 . n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 192 figure 7-36. timing of one-shot pulse output operation with external trigger (with rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tm0n count value cr01n set value cr00n set value ti00n pin input inttm01n inttm00n to0n pin output set tmc0n to 08h (tm0n count starts) caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc0n2 and tmc0n3 bits. remark n < m n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 193 7.5 cautions for 16-bit timer/event counters 00 and 01 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 0n (tm0n) is started asynchronously to the count clock. figure 7-37. start timing of 16-bit timer counter 0n (tm0n) tm0n count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match between tm0n and cr00n) set 16-bit timer capture/compare registers 00n, 01n (cr00n, cr01n) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an event counter. (3) operation after compare register change during timer count operation if the value after 16-bit timer capture/compare register 00n (cr00n) is changed is smaller than that of 16-bit timer counter 0n (tm0n), tm0n continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr00n changes is smaller than that (n) before the change, it is necessary to restart the timer after changing cr00n. figure 7-38. timings after change of compare register during timer count operation cr00n nm count clock tm0n count value x ? 1 x ffffh 0000h 0001h 0002h remark n > x > m n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 194 (4) capture register data retention timing if the valid edge of the ti00n pin is input during 16-bit timer capture/compare register 01n (cr01n) read, cr01n performs a capture operation. however, the value read at this time is not guaranteed. the interrupt request flag (tmif01n) is set upon detection of the valid edge. figure 7-39. capture register data retention timing count clock tm0n count value edge input interrupt request flag capture read signal cr01n interrupt value n n + 1 n + 2 m m + 1 m + 2 xn + 2 capture, but read value is not guaranteed capture m + 1 (5) valid edge setting set the valid edge of the ti00n pin after setting bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n (tmc0n) to 0, 0, respectively, and then stopping timer operation. the valid edge is set using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). (6) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt0n bit to 1. do not output the one-shot pulse again until inttm00n, which occurs upon a match with the cr00n register, or inttm01n, which occurs upon a match with the cr01n register, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the ti00n pin or its alternate function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti00n pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 195 (7) operation of ovf0n flag <1> the ovf0n flag is set to 1 in the following case. when of the following modes: the mode in which clear & start occurs on a match between tm0n and cr00n, the mode in which clear & start occurs on a ti0n valid edge, or the free-running mode, is selected cr00n is set to ffffh tm0n is counted up from ffffh to 0000h. figure 7-40. operation timing of ovf0n flag count clock cr00n tm0n ovf0n inttm00n ffffh fffeh ffffh 0000h 0001h <2> even if the ovf0n flag is cleared before the next count clock (before tm0n becomes 0001h) after the occurrence of tm0n overflow, the ovf0n flag is re-set newly and clear is disabled. (8) conflicting operations conflict between the read period of the 16-bit timer capture/compare register (cr00n/cr01n) and capture trigger input (cr00n/cr01n used as capture register) capture trigger input has priority. the data read from cr00n/cr01n is undefined. (9) timer operation <1> even if 16-bit timer counter 0n (tm0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (cr01n). <2> regardless of the cpu ? s operation mode, when the timer stops, the input signals to the ti00n/ti01n pins are not acknowledged. <3> the one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the ti00n valid edge. in the mode in which clear & start occurs on a match between the tm0n register and cr00n register, one-shot pulse output is not possible because an overflow does not occur. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 7 16-bit timer/event counters 00 and 01 preliminary user ? s manual u15947ej1v1ud 196 (10) capture operation <1> if ti00n valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for ti00n is not possible. <2> to ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0n (prm0n). <3> the capture operation is performed at the falling edge of the count clock. an interrupt request input (inttm00n/inttm01n), however, is generated at the rise of the next count clock. (11) compare operation <1> when the 16-bit timer capture/compare register (cr00n/cr01n) is overwritten during timer operation, a match interrupt may be generated or a clear operation may not be performed normally if that value is close to or larger than the timer value. <2> a capture operation may not be performed for cr00n/cr01n set in compare mode even if a capture trigger has been input. (12) edge detection <1> if the ti00n or ti01n pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti00n or ti01n pin to enable the 16-bit timer counter 0n (tm0n) operation, a rising edge is detected immediately after the operation is enabled. be careful therefore when pulling up the ti00n or ti01n pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to remove noise differs when the ti00n valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 0n (prm0n). the capture operation is started only after a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
preliminary user?s manual u15947ej1v1ud 197 chapter 8 8-bit timer/event counters 50 and 51 8.1 functions of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. figure 8-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p17 f x /2 2 f x /2 6 f x /2 8 f x /2 13 f x f x /2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p17 selector 8-bit timer counter 50 (tm50) selector
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 198 figure 8-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/p33/intp4 f x /2 4 f x /2 6 f x /2 8 f x /2 12 f x f x /2 match mask circuit ovf clear 3 selector tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/p33/intp4 selector 8-bit timer counter 51 (tm51) selector
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 199 8.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer output 1 (to5n) control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) note or port mode register 3 (pm3) note note see figure 4-11 block diagram of p16 and p17 and figure 4-14 block diagram of p33 . (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that counts the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. when the count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, the count value is cleared to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n. (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bit memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (inttm5n) is generated if they match. in pwm mode, when the to5n pin becomes active due to a tm5n overflow and the values of tm5n and cr5n match, the to5n pin becomes inactive. the value of cr5n can be set within 00h to ffh. cautions 1. in the mode in which clear & start occurs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 200 8.3 registers controlling 8-bit timer/event counters 50 and 51 the following three registers are used to control 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 1 (pm1) or port mode register 3 (pm3) (1) timer clock selection register 5n (tcl5n) this register sets the count clock of 8-bit timer/event counter 5n and the valid edge of ti5n input. tcl5n can be set by an 8-bit memory manipulation instruction. reset input clears tcl5n to 00h. remark n = 0, 1 figure 8-3. format of timer clock selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol76543210 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 010f x (10 mhz) 011f x /2 (5 mhz) 100f x /2 2 (2.5 mhz) 101f x /2 6 (156.25 khz) 110f x /2 8 (39.06 khz) 111f x /2 13 (1.22 khz) cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz.
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 201 figure 8-4. format of timer clock selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol76543210 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 010f x (10 mhz) 011f x /2 (5 mhz) 100f x /2 4 (625 khz) 101f x /2 6 (156.25 khz) 110f x /2 8 (39.06 khz) 111f x /2 12 (2.44 khz) cautions 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz.
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 202 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip-flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0, 1 figure 8-5. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w symbol76543210 tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (to50 pin outputs the low level) 1 output enabled
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 203 figure 8-6. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w symbol76543210 tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (to51 pin outputs the low level) 1 output enabled cautions 1. to clear tce5n to 0, set the interrupt mask flag (tmmk5n) to 1 beforehand. otherwise, an interrupt may occur when tce5n is cleared. tce5n is cleared to 0 as follows. tmmk5n = 1; mask set tce5n = 0; timer clear tmif5n = 0; interrupt request flag clear tmmk5n = 0; mask clear tce5n = 1; timer start 2. the settings of lvs5n and lvr5n are valid in other than pwm mode. 3. do not rewrite tmc5n1 and toe5n simultaneously. 4. when switching to the pwm mode, do not rewrite tm5n6 and lvs5n or lvr5n simultaneously. 5. to rewrite tmc5n6, stop operation beforehand. ? ? ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 204 remarks 1. in pwm mode, pwm output is made inactive by setting tce5n to 0. 2. if lvs5n and lvr5n are read after data is set, 0 is read. 3. the values of the tmc5n6, lvs5n, lvr5n, tmc5n1, and toe5n bits are reflected at the to5n pin regardless of the value of tce5n. 4. n = 0, 1 (3) port mode register 1 (pm1) and 3 (pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p33/to51/ti51 pins for timer output, set pm17 and pm33 and the output latches of p17 and p33 to 0. pm1 and pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. figure 8-7. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol76543210 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 8-8. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol76543210 pm3 0 0 0 0 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 205 8.4 operations of 8-bit timer/event counters 50 and 51 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) matches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). [setting] <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don ? t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. figure 8-9. interval timer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n to5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time interval time remark interval time = (n + 1) t n = 00h to ffh n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 206 figure 8-9. interval timer operation timing (2/2) (b) when cr5n = 00h t count clock tm5n cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n to5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 207 8.4.2 operation as external event counter the external event counter counts the number of external clock pulses to be input to ti5n by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit timer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the value of cr5n, inttm5n is generated. [setting] <1> set each register. ? tcl5n: select ti5n input edge. ti5n falling edge tcl5n = 00h ti5n rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 0000 00b = don ? t care) <2> when tce5n = 1 is set, the number of pulses input from ti5n is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. figure 8-10. external event counter operation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00 01 02 03 04 05 n ? 1 n 00 01 02 03 n count start remark n = 00h to ffh n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 208 8.4.3 square-wave output operation a square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals of the count value preset to cr5n by setting bit 0 (toe5n) of 8- bit timer mode control register 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register. ? set the port latches (p17 and p33) note and port mode registers (pm17 and pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f inversion enabled timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. frequency = f cnt /2 (n + 1) (n: 00h to ffh, f cnt : count clock) note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 caution do not write other values to cr5n during operation. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 209 figure 8-11. square-wave output operation timing count clock tmn count value cr5n to5n note count start 00h 01h 02h n ? 1n 00h 01h 02h n ? 1n 00h n note the initial value of to5n output can be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n).
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 210 8.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty ratio pulse determined by the value set to 8-bit timer compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. (1) pwm output basic operation [setting] <1> set each register. ? set the port latches (p17, p33) note and port mode registers (pm17, pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. set tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 [pwm output operation] <1> pwm output (output from to5n) outputs an inactive level after the count operation starts until an overflow occurs. <2> when an overflow occurs, the active level set in <1> above is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inactive level is output until an overflow occurs again. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 211 figure 8-12. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level active level inactive level (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n to5n l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 preliminary user ? s manual u15947ej1v1ud 212 (2) operation with cr5n changed figure 8-13. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is reloaded to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h <2> (b) cr5n value is changed from n to m after clock rising edge of ffh value is reloaded to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 <1> cr5n change (n m) <2> caution when reading from cr5n between <1> and <2> in figure 8-13, the value read differs from the actual value (read value: m, actual value of cr5n: n). 8.5 cautions for 8-bit timer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm51) are started asynchronously to the count clock. figure 8-14. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1
preliminary user?s manual u15947ej1v1ud 213 chapter 9 8-bit timers h0 and h1 9.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? 8-bit-accuracy interval timer ? 8-bit-accuracy pwm pulse generator mode ? 8-bit-accuracy carrier generator mode (8-bit timer h1 only) 9.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 consist of the following hardware. table 9-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn (tmhn) registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output two outputs (tohn) control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note note 8-bit timer h1 only remark n = 0, 1 figures 9-1 and 9-2 show the block diagrams.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u15947ej1v1ud 214 figure 9-1. block diagram of 8-bit timer h0 match internal bus tmhe0 cks02 cks01 cks00 tmmd01tmmd00 tolev0 toen0 8-bit timer h mode control register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder toh0/p15 inttmh0 selector f x f x /2 f x /2 2 f x /2 6 f x /2 10 to50/ti50/p17 interrupt generator output controller level inversion 1 0 f/f r 8-bit timer counter h0 (tmh0) pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register 00 (cmp00) selector figure 9-2. block diagram of 8-bit timer h1 tmhe1 cks12 cks11 cks10 tmmd11tmmd10 tolev1 toen1 toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 1 0 f/f r 3 2 rmc1 nrzb1 nrz1 match 8-bit timer h mode control register 1 (tmhmd1) 8-bit timer h compare register 11 (cmp11) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal 8-bit timer h compare register 01 (cmp01) 8-bit timer counter h1 (tmh1) clear selector internal bus reload/ interrupt control carrier generator mode signal
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 215 (1) 8-bit timer h compare register 0n (cmp0n) this register can be read/written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. cmp0n after reset: 00h r/w address: ff18h, ff1ah 7 6 5 4 32 1 0 caution this register cannot be rewritten during timer count operation. (2) 8-bit timer h compare register 1n (cmp1n) this register can be read/written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. cmp1n after reset: 00h r/w address: ff19h, ff1bh 7 6 5 4 32 1 0 the cmp1n register can be rewritten during timer count operation. an interrupt request signal (inttmhn) is generated if the values of the timer counter and cmp1n register match after setting the cmp1n register. the timer counter value is cleared at the same time. if the cmp1n register value is rewritten during timer operation, reloading is performed at the timing at which the counter value and cmp1n register value match. if the transfer timing and writing from cpu to cmp1n register conflict, transfer is not performed. caution in the pwm pulse generator mode and carrier generator mode, be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). remark n = 0, 1 9.3 registers controlling 8-bit timers h0 and h1 8-bit timers h0 and h1 are controlled by 8-bit timer h mode registers 0 and 1 (tmhmd0, tmhmd1) and 8-bit timer h carrier control register 1 (tmcyc1) note . note 8-bit timer h1 only (1) 8-bit timer h mode registers 0 and 1 (tmhmd0, tmhmd1) these registers control the mode of timer h. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 216 figure 9-3. format of 8-bit timer h mode register 0 (tmhmd0) tmhe0 stops timer count operation enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f x f x /2 f x /2 2 f x /2 6 f x /2 10 to50 cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 (10 mhz) (5 mhz) (2.5 mhz) (156.25 khz) (9.77 khz) count clock (f cnt ) selection setting prohibited other than above interval timer mode pwm pulse generator mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above 7 6 5 4 32 1 0 cautions 1. when tmhe0 = 1, setting the other bits of the tmhmd0 register is prohibited. 2. in the pwm pulse generator mode, be sure to set 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to the cmp10 register). remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u15947ej1v1ud 217 figure 9-4. format of 8-bit timer h mode register 1 (tmhmd1) tmhe1 stops timer count operation enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock (f cnt ) selection setting prohibited other than above interval timer mode carrier generator mode pwm pulse generator mode setting prohibited tmmd11 0 0 1 tmmd10 0 1 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control other than above 7 6 5 4 32 1 0 cautions 1. when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. 2. in the pwm pulse generator mode and carrier generator mode, be sure to set 8-bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 3. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. remarks 1. f x : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency 3. figures in parentheses apply to operation at f x = 10 mhz, f r = 240 khz (typ.).
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 218 (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-5. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note low-level output high-level output low-level output carrier pulse output rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag note bit 0 is read-only.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 219 9.4 operation of 8-bit timers h0 and h1 9.4.1 operation as interval timer when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 9-6. register setting in interval timer mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ? compare value (n) <2> count operation starts when tmhen = 1. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval timer = (n +1)/f cnt <4> subsequently, the inttmhn signal is generated at the same interval. to stop the count operation, set tmhen to 0. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 220 (2) timing chart the timing in interval timer mode is shown below. figure 9-7. timing of interval timer operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bit to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by setting the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 00h to ffh
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 221 figure 9-7. timing of interval timer operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 222 9.4.2 operation as pwm pulse generator in pwm mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). rewriting the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the duty of timer output (tohn). rewriting the cmp1n register during timer operation is possible. the operation in pwm mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> set each register. figure 9-8. register setting in pwm pulse generator mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) < ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare register that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and tohn output becomes active. at the same time, the compare register to be compared with 8-bit timer counter hn is changed from the cmp0n register to the cmp1n register.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 223 <4> when 8-bit timer counter hn and the cmp1n register match, tohn output becomes inactive and the compare register to be compared with 8-bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty ratio can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty ratio are as follows. pwm pulse output cycle = (n+1)/f cnt duty ratio = inactive width : active width = (m + 1) : (n ? m) cautions 1. in pwm mode, three operation clocks (signal selected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). (2) timing chart the operation timing in pwm mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) < ffh remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 224 figure 9-9. operation timing in pwm pulse generator mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains inactive (when tolevn = 0). <2> when the values of 8-bit timer counter hn and the cmp0n register match, the tohn output level is inverted, the value of 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of 8-bit timer counter hn and the cmp1n register match, the level of the tohn output is returned. at this time, the 8-bit timer counter value is not cleared and the inttmhn signal is not output. <4> setting the tmhen bit to 0 during timer hn operation makes the inttmhn signal and tohn output inactive. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 225 figure 9-9. operation timing in pwm pulse generator mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 226 figure 9-9. operation timing in pwm pulse generator mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 227 figure 9-9. operation timing in pwm pulse generator mode (4/4) (e) operation by changing cmp1n (cmp1n = 01h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp1n 01h a5h 03h 01h (03h) <1> <3> <4> <2> <2>' <5> <6> <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, the tohn output remains inactive (when tolevn = 0). <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output becomes active, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter hn and the cmp1n register before the change match, the value is transferred to the cmp1n register and the cmp1n register value is changed (<2> ? ). however, three count clocks or more are required from when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cmp1n register after the change match, the tohn output becomes inactive. 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <6> setting the tmhen bit to 0 during timer hn operation makes the inttmhn signal and tohn output inactive. remark n = 0, 1
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 228 9.4.3 carrier generator mode operation (8-bit timer h1 only) the carrier clock generated by 8-bit timer h1 is output in the cycle set by 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the toh1 output. in carrier generator mode, the connection between 8-bit timer h1 and 8-bit timer/event counter 51 is as shown below. figure 9-10. example of connection between 8-bit timer h1 and 8-bit timer/event counter 51 8-bit timer/event counter 51 prescaler cpu intc inttm51 inttm51 inttm5h1 inttmh1 8-bit timer h1 to51 toh1 selector tmmd10, tmmd11 (1) carrier generation in carrier generator mode, 8-bit timer h compare register 01 (cmp01) generates a low-level width carrier pulse waveform and 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during 8-bit timer h1 operation is possible but rewriting the cmp01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request signal (inttm51) of 8-bit timer/event counter 51 and the nrz1 and rmc1 bits of the 8-bit timer h carrier control register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrz1 bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u15947ej1v1ud 229 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuration. the nrz1 bit is read-only but the nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrzb1 bit to the nrz1 bit is as shown below. figure 9-11. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> note <2> <1> the inttm51 signal is synchronized with the count clock of 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is transferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. note when 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. caution do not rewrite the nrzb1 bit again until at least the second clock after it has been rewritten, or else the transfer from the nrzb1 bit to the nrz1 bit is not guaranteed.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 230 (3) usage outputs an arbitrary carrier clock from the toh1 pin. <1> set each register. figure 9-12. register setting in carrier generator mode (i) setting 8-bit timer h mode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled timer output level inversion setting carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 0/1 tmmd10 tolev1 toen1 cksh11 cksh12 tmhe1 tmhmd1 cksh10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? refer to 8.3 registers controlling 8-bit timer/event counters 50 and 51 . <2> when tmhe1 = 1, 8-bit timer h1 starts counting. <3> when tce51 of 8-bit timer mode control register 51 (tmc51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first compare register to be compared is the cmp01 register. when the count value of 8-bit timer counter h1 and the cmp01 register value match, the inttmh1 signal is generated, 8-bit timer counter h1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. <5> when the count value of 8-bit timer counter h1 and the cmp11 register value match, the inttmh1 signal is generated, 8-bit timer counter h1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> when the nrz1 bit is high level, a carrier clock is output from the toh1 pin. <9> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, set tmhe1 to 0.
chapter 9 8-bit timers h0 and h1 preliminary user?s manual u15947ej1v1ud 231 if the setting value of the cmp01 register is 1, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty ratio are as follows. carrier clock output cycle = (1 + m + 2)/f cnt duty ratio = high-level width : low-level width = ( m + 1) : (1 + 1) cautions 1. be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. (4) timing chart the carrier output control timing is shown below. cautions 1. set the values of the cmp01 and cmp11 registers in a range of 01h to ffh. 2. in the carrier generator mode, three operating clocks (signal selected by cksh12 to cksh10 bits of tmhmd1 register) or more are required from when the cmp11 register value is changed to when the value is transferred to the register. 3. be sure to set the rmc1 bit before the count operation is started.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 232 figure 9-13. carrier generator mode operation timing (1/3) (a) operation when cmp01 = 1, cmp11 = 1 cmp01 cmp11 tmhe1 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm51 count value cr51 tce51 toh1 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l <1> <2> <3> <4> <5> <6> <7> 8-bit timer h1 count clock 8-bit timer counter h1 count value <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer h1 starts a count operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level.
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 233 figure 9-13. carrier generator mode operation timing (2/3) (b) operation when cmp01 = 1, cmp11 = m (operation when carrier clock phase is asynchronous to nrz1 phase) n l cmp01 cmp11 tmhe1 inttmh1 carrier clock tm51 count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m cr51 tce51 toh1 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l <1> <2> <3> <4> <5> <6> <7> 8-bit timer 51 count clock 8-bit timer h1 count clock 8-bit timer counter h1 count value <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer h1 starts a count operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> when the carrier clock phase becomes asynchronous to the nrz1 bit phase, a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
chapter 9 8-bit timers h0 and h1 preliminary user ? s manual u15947ej1v1ud 234 figure 9-13. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3> ? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, 8-bit timer h1 starts a count operation. at that time, the carrier clock is held at the inactive level. <2> when the count value of 8-bit timer counter h1 matches the cmp01 register value, 8-bit timer counter h1 is cleared and the inttmh1 signal is output. <3> the cmp11 register can be rewritten during 8-bit timer h1 operation, however, the changed value (l) is latched. the cmp11 register is changed when the count value of 8-bit timer counter h1 and the cmp11 register value before the change (m) match (<3> ? ). <4> when the count value of 8-bit timer counter h1 and the cmp11 register value before the change (m) match, the inttmh1 signal is output, the carrier signal is inverted, and 8-bit timer counter h1 is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter h1 and the cmp11 register value match again is indicated by the value after the change (l).
preliminary user?s manual u15947ej1v1ud 235 chapter 10 watch timer 10.1 functions of watch timer the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. watch timer block diagram f x /2 7 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 f w clear 11-bit prescaler clear 5-bit counter watch timer operation mode register (wtm) internal bus selector selector selector selector remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 236 (1) watch timer when the x1 input clock or subsystem clock is used, interrupt requests (intwt) are generated at preset intervals. table 10-1. watch timer interrupt time interrupt time when operated at f xt = 32.768 khz when operated at f x = 10 mhz 2 4 /f w 488 s 205 s 2 5 /f w 977 s 410 s 2 13 /f w 0.25 s 0.105 s 2 14 /f w 0.5 s 0.210 s remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (2) interval timer interrupt requests (intwti) are generated at preset time intervals. table 10-2. interval timer interval time interval time when operated at f xt = 32.768 khz when operated at f x = 10 mhz 2 4 /f w 488 s 205 s 2 5 /f w 977 s 410 s 2 6 /f w 1.95 ms 820 s 2 7 /f w 3.91 ms 1.64 ms 2 8 /f w 7.81 ms 3.28 ms 2 9 /f w 15.6 ms 6.55 ms 2 10 /f w 31.2 ms 13.1 ms 2 11 /f w 62.4 ms 26.2 ms remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 237 10.2 configuration of watch timer the watch timer consists of the following hardware. table 10-3. watch timer configuration item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) 10.3 register controlling watch timer the watch timer is controlled by the watch timer operation mode register (wtm). ? ? ? ? watch timer operation mode register (wtm) this register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h.
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 238 figure 10-2. format of watch timer operation mode register (wtm) address: ff6fh after reset: 00h r/w symbol76543210 wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (78.125 khz) 1f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0002 4 /f w 0012 5 /f w 0102 6 /f w 0112 7 /f w 1002 8 /f w 1012 9 /f w 1102 10 /f w 1112 11 /f w wtm3 wtm2 interrupt time selection 002 14 /f w 012 13 /f w 102 5 /f w 112 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1start wtm0 watch timer operation enable 0 operation stop (clear both prescaler and timer) 1 operation enable caution do not change the count clock and interval time (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : x1 input clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f x = 10 mhz, f xt = 32.768 khz.
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 239 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request (intwt) at a specific time interval by using the x1 input clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1, the count operation starts. when these bits are set to 0, the 5-bit counter is cleared and the count operation stops. when the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by setting wtm1 to 0. in this case, however, the 11-bit prescaler is not cleared. therefore, an error up to 2 11 1/f w seconds occurs in the first overflow (intwt) after zero-second start. the interrupt request is generated at the following time intervals. table 10-4. watch timer interrupt time wtm3 wtm2 interrupt time selection when operated at f xt = 32.768 khz (wtm7 = 1) when operated at f x = 10 mhz (wtm7 = 0) 002 14 /f w 0.5 s 0.210 s 012 13 /f w 0.25 s 0.105 s 102 5 /f w 977 s 410 s 112 4 /f w 488 s 205 s remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 240 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt requests (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count operation starts. when this bit is set to 0, the count operation stops. table 10-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f xt = 32.768 khz (wtm7 = 1) when operated at f x = 10 mhz (wtm7 = 0) 0002 4 /f w 488 s 205 s 0012 5 /f w 977 s 410 s 0102 6 /f w 1.95 ms 820 s 0112 7 /f w 3.91 ms 1.64 ms 1002 8 /f w 7.81 ms 3.28 ms 1012 9 /f w 15.6 ms 6.55 ms 1102 10 /f w 31.2 ms 13.1 ms 1112 11 /f w 62.4 ms 26.2 ms remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency
chapter 10 watch timer preliminary user ? s manual u15947ej1v1ud 241 figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock f w /2 11 watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) n t n t caution when operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the specification made with bit 3 (wtm3) of wtm. this is because there is a delay of one 11-bit prescaler output cycle until the 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. remark f w : watch timer clock frequency n: the number of times of interval timer operations figures in parentheses are for operation with f w = 32.768 khz (wtm7 = 1, wtm3, wtm2 = 0, 0)
preliminary user?s manual u15947ej1v1ud 242 chapter 11 watchdog timer 11.1 functions of watchdog timer the watchdog timer detects an inadvertent program loop. if a program loop is detected, an internal reset signal (wdtres) is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, refer to chapter 22 reset function . table 11-1. loop detection time of watchdog timer loop detection time during ring-osc clock operation during x1 input clock operation f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz the operation mode of the watchdog timer (wdt) is switched according to the mask option setting of the on-chip ring-osc as shown in table 11-2.
chapter 11 watchdog timer preliminary user?s manual u15947ej1v1ud 243 table 11-2. mask option setting and watchdog timer operation mode mask option ring-osc cannot be stopped ring-osc can be stopped by software watchdog timer clock source fixed to f r note 1 . ? selectable by software (f xp , f r or stopped) ? when reset is released: f r operation after reset operation starts with the maximum interval (f r /2 18 ). operation starts with maximum interval (f r /2 18 ). operation mode selection the interval can be changed only once. the clock selection/interval can be changed only once. features ? the watchdog timer cannot be stopped. ? current in stop mode 10 a the watchdog timer can be stopped in standby mode note 2 . notes 1. as long as power is being supplied, ring-osc oscillation cannot be stopped (except in the reset period). 2. clock supply to the watchdog timer is stopped in accordance with the watchdog timer clock source as follows: <1> when the clock source is f xp clock supply to the watchdog timer is stopped while f xp is stopped, during halt/stop instruction execution, and during the oscillation stabilization time. <2> when the clock source is f r clock supply to the watchdog timer is stopped if f r is stopped by software before stop instruction execution when the cpu clock is f xp and during halt/stop instruction execution. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 11.2 configuration of watchdog timer the watchdog timer consists of following hardware. table 11-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) = . .
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 244 figure 11-1. block diagram of watchdog timer f r /2 2 clock input controller output controller wdtres (internal reset signal) wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter f xp /2 13 to f xp /2 20 or f r /2 11 to f r /2 18 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 3 2 clear mask option (to set "ring-osc cannot be stopped" or "ring-osc can be stopped by software") 11.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. reset input sets this register to 67h.
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 245 figure 11-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff98h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 ring-osc clock (f r ) 0 1 x1 input clock (f xp ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during ring-osc clock operation during x1 input clock operation 000f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) 001f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) 010f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) 011f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) 100f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) 101f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) 110f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) 111f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) notes 1. if ? ring-osc cannot be stopped ? is specified by a mask option, this cannot be set. the ring- osc clock will be selected no matter what value is written. 2. reset is released at the maximum cycle (wdcs2, 1, 0 = 1, 1, 1). cautions 1. if data is written to wdtm, a wait cycle is generated. do not write data to wdtm when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait. 2. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?ring-osc cannot be stopped? is selected by a mask option, other values are ignored). 3. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing attempted a second time, an internal reset signal is generated. 4. wdtm cannot be set by a 1-bit memory manipulation instruction. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. : don ? t care 4. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 246 (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 9ah. figure 11-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. 2. if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated (an error occurs in the assembler). 3. the value read from wdte is 9ah (this differs from the written value (ach)). 11.4 operation of watchdog timer 11.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by mask option the operation clock of watchdog timer is fixed to the ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: ring-osc clock ? cycle: f r /2 18 (1.09 seconds: at operation with f r = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2 . ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are executed, writing ach to wdte clears the count to 0, enabling recounting. notes 1. the operation clock (ring-osc clock) cannot be changed. if any value is written to bits 3 and 4 (wdcs3, wdcs4) of wdtm, it is ignored. 2. as soon as wdtm is written, the counter of the watchdog timer is cleared. caution in this mode, operation of the watchdog timer absolutely cannot be stopped even during stop instruction execution. for 8-bit timer h1 (tmh1), a division of the ring-osc can be selected as the count source, so clear the watchdog timer using the interrupt request of tmh1 before the watchdog timer overflows. if this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after stop instruction execution.
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 247 11.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option the operation clock of the watchdog timer can be selected as either the ring-osc clock or the x1 input clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: ring-osc clock oscillation frequency (f r ) ? cycle: f r /2 18 (1.09 seconds: at operation with f r = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2, 3 . ? operation clock: any of the following can be selected using bits 3 and 4 (wdcs3 and wdcs4). ring-osc clock (f r ) x1 input clock (f xp ) watchdog timer operation stopped ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are executed, writing ach to wdte clears the count to 0, enabling recounting. notes 1. as soon as wdtm is written, the counter of the watchdog timer is cleared. 2. set bits 7, 6, and 5 to 0, 1, 1, respectively. if other values are set, the watchdog timer cannot be operated (an error occurs in the assembler). 3. if the watchdog timer is stopped by setting wdcs4 and wdcs3 to 1 and , respectively, an internal reset signal is not generated even if the following processing is performed. ? wdtm is written a second time. ? a 1-bit memory manipulation instruction is executed to wdte. ? a value other than ach is written to wdte. caution in this mode, watchdog timer operation is stopped during halt/stop instruction execution. after halt/stop mode is released, counting is started again using the operation clock of the watchdog timer set before halt/stop instruction execution by wdtm. at this time, the counter is not cleared to 0. for the watchdog timer operation during stop mode and halt mode in each status, refer to 11.4.3 watchdog timer operation in stop mode and 11.4.4 watchdog timer operation in halt mode.
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 248 11.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during stop instruction execution regardless of whether the x1 input clock or ring-osc clock is being used. (1) when the cpu clock and the watchdog timer operation clock are the x1 input clock (f xp ) when the stop instruction is executed when stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (osts) and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 11-4. operation in stop mode (cpu clock and wdt operation clock: x1 input clock) watchdog timer operating operation stopped operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register)
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 249 (2) when the cpu clock is the x1 input clock (f xp ) and the watchdog timer operation clock is the ring-osc clock (f r ) when the stop instruction is executed when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 11-5. operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) operating operation stopped
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 250 (3) when the cpu clock is the ring-osc clock (f r ) and the watchdog timer operation clock is the x1 input clock (f xp ) when the stop instruction is executed when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. <1> the oscillation stabilization time set by the oscillation stabilization time select register (osts) elapses. <2> the cpu clock is switched to the x1 input clock (f xp ). figure 11-6. operation in stop mode (cpu clock: ring-osc clock, wdt operation clock: x1 input clock) <1> timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (osts) has elapsed watchdog timer operating operation stopped operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) <2> timing when counting is started after the cpu clock is switched to the x1 input clock (f xp ) operating operation stopped operating f r f xp f r f xp note cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) normal operation (x1 input clock) cpu clock oscillation stopped stop oscillation stabilization time (set by osts register) watchdog timer note confirm the oscillation stabilization time of f xp using the oscillation stabilization time counter status register (ostc).
chapter 11 watchdog timer preliminary user ? s manual u15947ej1v1ud 251 (4) when cpu clock and watchdog timer operation clock are the ring-osc clocks (f r ) during stop instruction execution when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 11-7. operation in stop mode (cpu clock and wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) operating operation stopped 11.4.4 watchdog timer operation in halt mode (when ? ring-osc can be stopped by software ? is selected by mask option) the watchdog timer stops counting during halt instruction execution regardless of whether the cpu clock is the x1 input clock (f xp ), ring-osc clock (f r ), or subsystem clock (f xt ), or whether the operation clock of the watchdog timer is the x1 input clock (f xp ) or ring-osc clock (f r ). after halt mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 11-8. operation in halt mode watchdog timer operating f r f xp cpu operation normal operation operating halt operation stopped f xt normal operation
preliminary user?s manual u15947ej1v1ud 252 chapter 12 clock output/buzzer output controller 12.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output. in addition, the buzzer output is intended for square-wave output of buzzer frequency selected with cks. figure 12-1 shows the block diagram of clock output/buzzer output controller. figure 12-1. block diagram of clock output/buzzer output controller 8 4 bzoe bcs0, bcs1 clock controller cloe buz/busy0/intp7/p141 pcl/intp6/p140 internal bus selector bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 clock output selection register (cks) selector prescaler f x /2 10 to f x /2 13 f x to f x /2 7 f xt f x
chapter 12 clock output/buzzer output controller preliminary user ? s manual u15947ej1v1ud 253 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller consists of the following hardware. table 12-1. clock output/buzzer output controller configuration item configuration control registers clock output selection register (cks) port mode register 14 (pm14) note note see figure 4-23 block diagram of p140 and p141 . 12.3 register controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 14 (pm14) (1) clock output selection register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h.
chapter 12 clock output/buzzer output controller preliminary user?s manual u15947ej1v1ud 254 figure 12-2. format of clock output selection register (cks) address: ff40h after reset: 00h r/w symbol76543210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circuit operation stopped. buz fixed to low level. 1 clock division circuit operation enabled. buz output enabled. bcs1 bcs0 buz output clock selection 00f x /2 10 (9.77 khz) 01f x /2 11 (4.88 khz) 10f x /2 12 (2.44 khz) 11f x /2 13 (1.22 khz) cloe pcl output enable/disable specification 0 clock division circuit operation stopped. pcl fixed to low level. 1 clock division circuit operation enabled. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0000f x (10 mhz) 0001f x /2 (5 mhz) 0010f x /2 2 (2.5 mhz) 0011f x /2 3 (1.25 mhz) 0100f x /2 4 (625 khz) 0101f x /2 5 (312.5 khz) 0110f x /2 6 (156.25 khz) 0111f x /2 7 (78.125 khz) 1000f xt (32.768 khz) other than above setting prohibited remarks 1. f x : x1 input clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f x = 10 mhz or f xt = 32.768 khz.
chapter 12 clock output/buzzer output controller preliminary user ? s manual u15947ej1v1ud 255 (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pcl pin for clock output and the p141/busy0/intp7/buz pin for buzzer output, set pm140, pm141 and the output latch of p140, p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm14 to ffh. figure 12-3. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol76543210 pm14 1 1 pm145 pm144 pm143 pm142 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 12 clock output/buzzer output controller preliminary user ? s manual u15947ej1v1ud 256 12.4 clock output/buzzer output controller operations 12.4.1 clock output operation the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as shown in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing high level of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
preliminary user?s manual u15947ej1v1ud 257 chapter 13 a/d converter 13.1 functions of a/d converter the a/d converter converts an analog input signal into a digital value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following two functions. (1) 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani7. each time an a/d conversion operation ends, an interrupt request (intad) is generated. (2) power-fail detection function this function is used to detect a voltage drop in a battery. the a/d conversion result (adcr register value) and power-fail comparison threshold register (pft) value are compared. intad is generated only when a comparative condition has been matched.
chapter 13 a/d converter preliminary user?s manual u15947ej1v1ud 258 figure 13-1. block diagram of a/d converter sample & hold circuit series resistor string successive approximation register (sar) adcs fr2 fr1 adce controller voltage comparator a/d conversion result register (adcr) av ref (can be used as analog power supply) av ss intad internal bus a/d converter mode register (adm) tap selector selector ani0/p20 ani1/p21 ani2/p22 ani3/p23 fr0 ads1 ads0 analog input channel specification register (ads) 3 ads2 ani4/p24 ani5/p25 ani6/p26 ani7/p27 figure 13-2. block diagram of power-fail detection function selector pfen pfcm internal bus a/d converter pfcm pfen comparator power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) intad selector ani0/p20 ani1/p21 ani2/p22 ani3/p23 ads1 ads0 analog input channel specification register (ads) ads2 ani4/p24 ani5/p25 ani6/p26 ani7/p27
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 259 13.2 configuration of a/d converter the a/d converter consists of the following hardware. table 13-1. configuration of a/d converter item configuration analog input 8 channels (ani0 to ani7) registers successive approximation register (sar) a/d conversion result register (adcr) control registers a/d converter mode register (adm) analog input channel specification register (ads) power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) (1) successive approximation register (sar) this register compares the analog input voltage value with the voltage tap (compare voltage) value applied from the series resistor string, and holds the result starting from the most significant bit (msb). when the result up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr) the adcr is 16-bit register that stores the a/d conversion result. the lower six bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register, and is stored in adcr in order starting from the most significant bit (msb). adcr can be read by a 16-bit memory manipulation instruction. reset input makes adcr undefined. figure 13-3. format of a/d conversion register (adcr) symbol address: ff08h, ff09h after reset: undefined r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is generated. do not read data from adcr when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 260 (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input with the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared with the analog input. (6) ani0 to ani7 pins these eight-channel analog input pins input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani7 are alternate-function pins that can also be used for digital input. cautions 1. observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher or a voltage of av ss or lower (even if within the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. 2. the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (7) av ref pin the av ref pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals based on a voltage between av ref and av ss . in a standby mode, the current flowing into series resistor strings can be reduced by changing the input voltage of the av ref pin to av ss level. it can also be used as the analog power supply. when the a/d converter is used, be sure to use the av ref pin for the power supply. caution a series resistor string of several tens of k ? ? ? ? is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. (8) av ss pin the av ss pin is the gnd potential pin for the a/d converter. always use the av ss pin at the same potential as the v ss0 pin, even when the a/d converter is not used.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 261 13.3 registers controlling a/d converter the following four registers are used to control the a/d converter. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power-fail comparison mode register (pfm) ? power-fail comparison threshold register (pft) (1) a/d converter mode register (adm) this register sets the conversion time for analog input to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-4. format of a/d converter mode register (adm) 144 s note 1 120 s note 1 96 s 72 s 60 s 48 s adce 0 0 fr0 fr1 fr2 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 conversion time selection note 1 288/f x 240/f x 192/f x 144/f x 120/f x 96/f x setting prohibited fr2 0 0 0 1 1 1 other fr1 0 0 1 0 0 1 fr0 0 1 0 0 1 0 0 1 2 3 4 5 6 7 adm address: ff28h after reset: 00h r/w symbol 34.3 s 28.6 s 22.9 s 17.2 s 14.3 s 11.5 s note 1 28.8 s 24.0 s 19.2 s 14.4 s 12.0 s note 1 9.6 s note 1 f x = 8.38 mhz f x = 10 mhz boost reference voltage generator operation control note 2 stops operation of reference voltage generator enables operation of reference voltage generator adce 0 1 f x = 2 mhz notes 1. set so that the a/d conversion time is 14 s or longer but less than 100 s. 2. a booster circuit is incorporated to realize low-voltage operation. the operation of the circuit that generates the reference voltage for boosting is controlled by adce, and it takes 14 s from operation start to operation stabilization. therefore, when adcs is set to 1 after 14 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result.
chapter 13 a/d converter preliminary user?s manual u15947ej1v1ud 262 table 13-2. settings of adcs and adce adcs adce a/d conversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 13-5. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note 14 s or more is required for reference voltage stabilization. cautions 1. a/d conversion must be stopped before rewriting bits fr0 to fr2 to values other than the identical data. 2. for the sampling time of the a/d converter and the a/d conversion start delay time, refer to (11) in 13.6 cautions for a/d converter. 3. if data is written to adm, a wait cycle is generated. do not write data to adm when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait. remark f x : x1 input clock oscillation frequency
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 263 (2) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-6. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to set bits 3 to 7 of ads to 0. 2. if data is written to ads, a wait cycle is generated. do not write data to ads when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 264 (3) power-fail comparison mode register (pfm) the power-fail comparison mode register (pfm) is a register that controls the comparison operation. pfm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-7. format of power-fail comparison mode register (pfm) 0 0 0 0 0 0 pfcm pfen power-fail comparison enable stops power-fail comparison (used as a normal a/d converter) enables power-fail comparison (used for power-fail detection) pfen 0 1 power-fail comparison mode selection interrupt request signal (intad) generation no intad generation no intad generation intad generation adcr3 pft3 adcr3 < pft3 adcr3 pft3 adcr3 < pft3 pfcm 0 1 0 1 2 3 4 5 6 7 pfm address: ff2ah after reset: 00h r/w symbol caution if data is written to pfm, a wait cycle is generated. do not write data to pfm when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait. (4) power-fail comparison threshold register (pft) the power-fail comparison threshold register (pft) is a register that sets the threshold value when comparing the values with the a/d conversion result. 8-bit data in pft is compared to the higher 8 bits (ff09h) of the 10-bit a/d conversion result. pft can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-8. format of power-fail comparison threshold register (pft) pft0 pft1 pft2 pft3 pft4 pft5 pft6 pft7 0 1 2 3 4 5 6 7 pft address: ff2bh after reset: 00h r/w symbol caution if data is written to pft, a wait cycle is generated. do not write data to pft when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 265 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with analog input channel specification register (ads). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <6> next, bit 8 of sar is automatically set to 1, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) v dd ? bit 9 = 0: (1/4) v dd the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion result register (adcr) and then latched. at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution the first a/d conversion value immediately after a/d conversion operations start may not fall within the rating.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 266 figure 13-9. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to one of the adm, analog input channel specification register (ads), power-fail comparison mode register (pfm), or power-fail comparison threshold register (pft) during an a/d conversion operation, the conversion operation is initialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset input makes the a/d conversion result register (adcr) undefined.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 267 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (stored in the a/d conversion result register (adcr)) is shown by the following expression. adcr = int ( 1024 + 0.5) or (adcr ? 0.5) ? v in < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr: a/d conversion result register (adcr) value figure 13-10 shows the relationship between the analog input voltage and the a/d conversion result. figure 13-10. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref v in av ref av ref 1024 av ref 1024
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 268 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d conversion is executed. in addition, the following two functions can be selected by setting of bit 7 (pfen) of the power-fail comparison mode register (pfm). ? normal 10-bit a/d converter (pfen = 0) ? power-fail detection function (pfen = 1) (1) a/d conversion operation (when pfen = 0) by setting bit 7 (adcs) of the a/d converter mode register (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 0, the a/d conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/d conversion has started and when one a/d conversion has been completed, the next a/d conversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if ads is rewritten during a/d conversion, the a/d conversion under execution is suspended, and the a/d conversion of the newly selected analog input channel is started. if 0 is written to adcs of adm during a/d conversion, the conversion operation is immediately stopped. figure 13-11. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr intad (pfen = 0) conversion is stopped conversion result is not retained remarks 1. n = 0 to 7 2. m = 0 to 7
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 269 (2) power-fail detection function (when pfen = 1) by setting bit 7 (adcs) of the a/d converter mode register (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 1, the a/d conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ads) is started. when the a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr), the values are compared with power-fail comparison threshold register (pft), and an interrupt request signal (intad) is generated under the condition specified by bit 6 (pfcm) of pfm. <1> when pfen = 0 intad is generated at the end of each a/d conversion. <2> when pfen = 1 and pfcm = 0 the adcr and pft values are compared when a/d conversion ends and intad is only generated when adcr pft. <3> when pfen = 1 and pfcm = 1 the adcr and pft values are compared when a/d conversion ends and intad is only generated when adcr < pft. figure 13-12. power-fail detection (when pfen = 1 and pfcm = 0) a/d conversion adcr pft intad (pfen = 1) anin anin 80h 80h condition match first conversion note 7fh 80h anin anin note if the conversion result is not read before the end of the next conversion after intad is output, the result is replaced by the next conversion result. remark n = 0 to 7
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 270 the setting methods are described below. ? when used as a/d conversion operation <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> select the channel and conversion time using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <3> set bit 7 (adcs) of adm to 1. <4> an interrupt request signal (intad) is generated. <5> transfer the a/d conversion data to the a/d conversion result register (adcr). <6> change the channel using bits 2 to 0 (ads2 to ads0) of ads. <7> an interrupt request signal (intad) is generated. <8> transfer the a/d conversion data to the a/d conversion result register (adcr). <9> clear adcs to 0. <10> clear adce to 0. cautions 1. make sure the period of <1> to <3> is 14 s or more. 2. it is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. however, do not use the first conversion result after <3> in this case. 4. the period from <4> to <7> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <6> to <7> is the conversion time set using fr2 to fr0. ? when used as power-fail function <1> set bit 7 (pfen) of the power-fail comparison mode register (pfm). <2> set power-fail comparison condition using bit 6 (pfcm) of pfm. <3> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <4> select the channel and conversion time using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <5> set a threshold value to the power-fail comparison threshold register (pft). <6> set bit 7 (adcs) of adm to 1. <7> transfer the a/d conversion data to the a/d conversion result register (adcr). <8> adcr and pft are compared and an interrupt request signal (intad) is generated if the conditions match. <9> change the channel using bits 2 to 0 (ads2 to ads0) of ads. <10> transfer the a/d conversion data to the a/d conversion result register (adcr). <11> adcr and the power-fail comparison threshold register (pft) are compared and an interrupt request signal (intad) is generated if the conditions match. <12> clear adcs to 0. <13> clear adce to 0. cautions 1. make sure the period of <3> to <6> is 14 s or more. 2. it is no problem if order of <3>, <4>, and <5> is changed. 3. <3> can be omitted. however, do not use the first conversion result after <6> in this case. 4. the period from <7> to <11> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <9> to <11> is the conversion time set using fr2 to fr0.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 271 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-13. overall error figure 13-14. quantization error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 272 (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 ?? 001 to 0 ?? 010. (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale ? 3/2lsb) when the digital output changes from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indicates the difference between the actual measurement value and the ideal value. figure 13-15. zero-scale error figure 13-16. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref av ref ? 1 av ref ? 2 av ref ? 3 digital output (lower 3 bits) analog input (lsb) ideal line full-scale error figure 13-17. integral linearity error figure 13-18. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 273 (8) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. the sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time 13.6 cautions for a/d converter (1) current consumption in standby mode the a/d converter stops operating in the standby mode. at this time, the current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs) of the a/d converter mode register (adm) to 0). figure 13-19 shows how to reduce the current consumption in the standby mode. figure 13-19. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs (2) input range of ani0 to ani7 observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 274 (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon the end of conversion adcr read has priority. after the read operation, the new conversion result is written to adcr. old data can be read from adcr at the timing of (1) and new data can be read from adcr at the timing of (2) as shown in figure 13-20. a master-slave configuration is employed for transferring the a/d conversion result to adcr. figure 13-20. storing conversion result in adcr and timing of data read from adcr (1) timing to read old data internal clock intad master write signal a/d conversion (master) slave write signal adcr (slave) read data conversion end conversion result n conversion result n conversion result n conversion result n + 1 (2) timing to read new data internal clock intad master write signal a/d conversion (master) slave write signal adcr (slave) read data conversion end conversion result n conversion result n + 1 conversion result n + 1 conversion result n + 1 <2> conflict between adcr write and a/d converter mode register (adm) write or analog input channel specification register (ads) write adm or ads write has priority. adcr write is not performed, nor is the conversion end interrupt signal (intad) generated.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 275 (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani7. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 13-21, to reduce noise. figure 13-21. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 13-21 ). (7) av ref pin input impedance a series resistor string of several tens of 10 k ? is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 276 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrite. caution is therefore required since, at this time, when adif is read immediately after the ads rewrite, adif is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 13-22. timing of a/d conversion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr intad anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conversion starts may not fall within the rating. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. (10) a/d conversion result register (adcr) read operation when a write operation is performed to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. do not read adcr when the cpu is operating on the subsystem clock and oscillation of the x1 input clock is stopped.
chapter 13 a/d converter preliminary user ? s manual u15947ej1v1ud 277 (11) a/d converter sampling time and a/d conversion start delay time the a/d converter sampling time differs depending on the set value of the a/d converter mode register (adm). the delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 13-23 and table 13-3. figure 13-23. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time a/d conversion start delay time sampling time sampling timing intad adcs 1 or ads rewrite table 13-3. a/d converter sampling time and a/d conversion start delay time (adm set value) a/d conversion start delay time note fr2 fr1 fr0 conversion time sampling time min. max. 0 0 0 288/f x 40/f x 32/f x 36/f x 0 0 1 240/f x 32/f x 28/f x 32/f x 0 1 0 192/f x 24/f x 24/f x 28/f x 1 0 0 144/f x 20/f x 16/f x 18/f x 1 0 1 120/f x 16/f x 14/f x 16/f x 1 1 0 96/f x 12/f x 12/f x 14/f x other than above setting prohibited ??? note the a/d conversion start delay time is the time after wait period. for the wait function, refer to chapter 32 cautions for wait . remark f x : x1 clock oscillation frequency
preliminary user?s manual u15947ej1v1ud 278 chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not executed and can enable a reduction in the power consumption. for details, refer to 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. ? two-pin configuration t x d0: transmit data output pin r x b0: receive data input pin ? length of transfer data can be selected from 7 or 8 bits. ? dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? four operating clock inputs selectable ? fixed to lsb-first transfer cautions 1. the default value of the t x d0 pin is high level. exercise care when using the t x d0 pin as a port pin. 2. if clock supply to serial interface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before clock supply was stopped. the t x d0 pin also holds the value immediately before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power0 = 0, rxe0 = 0, and txe0 = 0. 3. set power0 = 1 and then set txe0 = 1 (transmission) or rxe0 = 1 (reception) to start communication. 4. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set.
chapter 14 serial interface uart0 preliminary user?s manual u15947ej1v1ud 279 14.2 configuration of serial interface uart0 serial interface uart0 consists of the following hardware. table 14-1. configuration of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface operation mode register 0 (asim0) asynchronous serial interface reception error status register 0 (asis0) baud rate generator control register 0 (brgc0)
chapter 14 serial interface uart0 preliminary user?s manual u15947ej1v1ud 280 t x d0/sck10/p10 intst0 r x d0/si10/p11 intsr0 f x /2 5 f x /2 3 f x /2 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) to50/ti50/p17 (tm50 output) registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit figure 14-1. block diagram of serial interface uart0
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 281 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data converted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the receive data is not transferred to rxb0. reset input or power0 = 0 sets this register to ffh. rxb0 can be read by an 8-bit memory manipulation instruction. no data can be written to this register. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. reset input, power0 = 0, or txe0 = 0 sets this register to ffh. txs0 can be written by an 8-bit memory manipulation instruction. this register cannot be read. caution do not write the next transmit data to txs0 before the transmission completion interrupt signal (intst0) is generated.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 282 14.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following three registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface reception error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) (1) asynchronous serial interface operation mode register 0 (asim0) this 8-bit register controls the serial transfer operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. figure 14-2. format of asynchronous serial interface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception. note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set. 4. be sure to set bit 0 to 1.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 283 figure 14-2. format of asynchronous serial interface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. clear the txe0 and rxe0 bits to 0 before rewriting the ps01, ps00, and cl0 bits. 2. make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 284 (2) asynchronous serial interface reception error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power0) and bit 5 (rxe0) of asim0 = 0. 00h is read when this register is read. figure 14-3. format of asynchronous serial interface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol76543210 asis000000pe0fe0ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 285 (3) baud rate generator control register 0 (brgc0) this register selects the base clock of serial interface uart0 and controls the baud rate. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. figure 14-4. format of baud rate generator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol76543210 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk ) selection 0 0 tm50 output (to50) 01f x /2 (5 mhz) 10f x /2 3 (1.25 mhz) 11f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 00 setting prohibited 010008f xclk /8 010019f xclk /9 0101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1101026f xclk /26 1101127f xclk /27 1110028f xclk /28 1111030f xclk /30 1111131f xclk /31 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate is the output clock of the 5-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to mdl00 bits (k = 8, 9, 10, ..., 31) 4. :don ? t care 5. figures in parentheses apply to operation at f x = 10 mhz
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 286 14.4 operation of serial interface uart0 this section explains the two modes of serial interface uart0. 14.4.1 operation stop mode in this mode, serial transfer cannot be executed, thus reducing the power consumption. in addition, the pins can be used as ordinary port pins in this mode. (1) register setting the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception. note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 287 14.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) register setting the uart mode is set by asynchronous serial interface operation mode register 0 (asim0), asynchronous serial interface reception error status register 0 (asis0), and baud rate generator control register 0 (brgc0). (a) asynchronous serial interface operation mode register 0 (asim0) this 8-bit register controls the serial transfer operations of serial interface uart0. asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set. 4. be sure to set bit 0 to 1.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 288 ps01 ps00 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. clear the txe0 and rxe0 bits to 0 before rewriting the ps01, ps00, and cl0 bits. 2. make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 289 (b) asynchronous serial interface reception error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power0) and bit 5 (rxe0) of asim0 = 0. 00h is read when this register is read. address: ff73h after reset: 00h r symbol76543210 asis000000pe0fe0ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 290 (2) communication operation (a) normal transmit/receive data format figure 14-5 shows the format of the transmit/receive data. figure 14-5. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 0 (asim0). figure 14-6. example of normal uart transmit/receive data format 1. data length: 8 bits, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity, stop bit: 2 bits, transfer data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, parity: none, stop bit: 1 bit, transfer data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 291 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ? 1 ? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ? 1 ? : 1 if transmit data has an even number of bits that are ? 1 ? : 0 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ? 1 ? is odd. if transmit data has an odd number of bits that are ? 1 ? : 0 if transmit data has an even number of bits that are ? 1 ? : 1 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ? 0 ? or ? 1 ? . (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 292 (c) transmission the t x d0 pin outputs a high level when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is set to 1. if bit 6 (txe0) of asim0 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to transmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the start bit is output from the t x d0 pin, followed by the rest of the data in order starting from the lsb. when transmission is completed, the parity and stop bits set by asim0 are appended and a transmission completion interrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 14-7 shows the timing of the transmission completion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 14-7. normal transmission completion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 293 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator starts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 14-8). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the stop bit has been received, the reception completion interrupt (intsr0) is generated and the data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) or a framing error (fe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr0) is generated after completion of reception. figure 14-8. reception completion interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. be sure to read receive buffer register 0 (rxb0) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchronous serial interface reception error status register 0 (asis0) before reading rxb0.
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 294 (e) reception error three types of errors may occur during reception: a parity error, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status register 0 (asis0) is set as a result of data reception, a reception error interrupt request (intsr0) is generated. which error has occurred during reception can be identified by reading the contents of asis0 in the reception error interrupt servicing (intsr0) (refer to table 14-2 ). the contents of asis0 are reset to 0 when asis0 is read. table 14-2. cause of reception error reception error cause value of asis0 parity error the parity specified for transmission does not match the parity of the receive data. 04h framing error stop bit is not detected. 02h overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). 01h (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14-9, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-9. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 295 14.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of baud rate generator ? base clock (clock) the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator control register 0 (brgc0) is supplied to each module when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is 1. this clock is called the base clock ? clock ? and its frequency is called f xclk . ? clock ? is fixed to low level when power0 = 0. ? transmission counter this counter stops, cleared to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, cleared to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 14-10. configuration of baud rate generator clock (f xclk ) selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 to50/ti50/p17 (tm50 output) f x /2 5 f x /2 f x /2 3 remark power0: bit 7 of asynchronous serial interface mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 296 (2) generation of serial clock a serial clock can be generated by using baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value of the 5-bit counter. (a) baud rate generator control register 0 (brgc0) this register selects the base clock of serial interface uart0 and controls the baud rate. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. address: ff71h after reset: 1fh r/w symbol76543210 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk ) selection 0 0 tm50 output (to50) 01f x /2 (5 mhz) 10f x /2 3 (1.25 mhz) 11f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 00 setting prohibited 010008f xclk /8 010019f xclk /9 0101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1101026f xclk /26 1101127f xclk /27 1110028f xclk /28 1111030f xclk /30 1111131f xclk /31 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate value is the output clock of the 5-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to mdl00 bits (k = 8, 9, 10, ..., 31) 4. :don ? t care 5. figures in parentheses apply to operation with f x = 10 mhz
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 297 (b) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of the brgc0 register (k = 8, 9, 10, ..., 31) (c) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock (clock) = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] f xclk 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 298 (3) example of setting baud rate table 14-3. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] 2400 ?? ? ? ?? ? ? 3 27 2425 1.03 4800 ?? ? ? 3 27 4850 1.03 3 14 4676 ? 2.58 9600 3 16 9766 1.73 3 14 9353 ? 2.58 2 27 9699 1.03 10400 3 15 10417 0.16 3 13 10072 ? 3.15 2 25 10475 0.72 19200 3 8 19531 1.73 2 27 19398 1.03 2 14 18705 ? 2.58 31250 2 20 31250 0 2 17 30809 ? 1.41 ?? ? ? 38400 2 16 39063 1.73 2 14 38796 ? 2.58 2 27 38796 1.03 76800 2 8 78125 1.73 1 27 77593 1.03 1 14 74821 ? 2.58 115200 1 22 113636 ? 1.36 1 18 116389 1.03 1 9 116389 1.03 153600 1 16 156250 1.73 1 14 149643 ? 2.58 ?? ? ? 230400 1 11 227273 ? 1.36 1 9 232778 1.03 ?? ? ? remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f x : x1 input clock oscillation frequency err: baud rate error
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 299 (4) permissible baud rate range during reception the permissible error from the baud rate at the transmission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-11. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax transfer rate of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible transfer rate maximum permissible transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-11, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (brgc0) after the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks
chapter 14 serial interface uart0 preliminary user ? s manual u15947ej1v1ud 300 minimum permissible transfer rate: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible transfer rate can be calculated as follows. 10 k + 2 21k ? 2 11 2 k2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-4. maximum/minimum permissible baud rate error division ratio (k) maximum permissible baud rate error minimum permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2
preliminary user?s manual u15947ej1v1ud 301 chapter 15 serial interface uart6 15.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not executed and can enable a reduction in the power consumption. for details, refer to 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) bus. the functions of this mode are outlined below. ? two-pin configuration t x d6: transmit data output pin r x b6: receive data input pin ? data length of transfer data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? twelve operating clock inputs selectable ? msb- or lsb-first transfer selectable ? inverted transmission operation ? tuning break field transmission from 13 to 20 bits ? more than 11 bits can be identified for tuning break field reception (sbf reception flag provided). cautions 1. the default value of the t x d6 pin is the high level. exercise care when using the t x d6 pin as a port pin. 2. the t x d6 output inversion function inverts only the transmission side and not the reception side. to use this function, the reception side must be ready for reception of inverted data (it must be able to recognize a low-level start bit). 3. if clock supply to serial interface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before clock supply was stopped. the t x d6 pin also holds the value immediately before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. 4. if data is continuously transmitted, the transfer rate from the stop bit to the next start bit is extended two clocks. however, this does not affect the result of transfer because the reception side initializes the timing when it has detected a start bit. do not use the continuous transmission function if the interface is incorporated in lin.
chapter 15 serial interface uart6 preliminary user?s manual u15947ej1v1ud 302 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, actuators, and sensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figures 15-1 and 15-2 outline the transmission and reception operations of lin. figure 15-1. lin transmission operation sleep bus tx6 intst6 note 4 wakeup signal frame tuning break field tuning field match field data field checksum field data field 8 bits note 3 note 1 13-bit note 2 sbf transmission 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. the tuning break field is output by hardware. the output width is equal to the bit length set by bits 5 to 3 (sbl62 to sbl60) of asynchronous serial interface control register 6 (asicl6). if the output width needs to be adjusted more accurately, use baud rate generator control register 6 (brgc6). 3. the wakeup signal frame is substituted by 80h transfer in the 8-bit mode. 4. intst6 is output on completion of each transmission. it is also output when sbf is transmitted.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 303 figure 15-2. lin reception operation sleep bus rx6 reception interrupt (intsr6) edge detection (intp0) capture timer data reception wakeup signal frame tuning break field tuning field match field data field data field checksum field disable enable disable enable note 1 note 3 note 4 13 bits note 2 sbf reception id reception sf reception data reception data reception note 5 notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when 11 bits or more of sbf have been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if less than 11 bits of sbf have been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of uart communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the value obtained from the capture timer, disable uart6 after sf reception, and then re-set baud rate generator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again. to perform a lin receive operation, use a configuration like the one shown in figure 15-3. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0). the length of the tuning break field transmitted from the lin master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated using the time and number of bits of the tuning break field. the input signal of the reception port input (rxd6) can be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without connecting rxd6 and intp0/ti000 externally.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 304 figure 15-3. port configuration for lin reception operation mpx rxd6 input intp0 input ti000 input p14/r x d6 p120/intp0 p00/ti000 port input switch control (isc0) 0: a output 1: b output a b q mpx port mode (pm14) a b q port latch (p14) mpx port mode (pm120) a b q port latch (p120) mpx port input switch control (isc1) 0: a output 1: b output a b q mpx port mode (pm00) a b q port latch (p00) remark isc0, isc1: bits 0 and 1 of the input switch control register (isc) (see figure 4-29 ) the resources used in the lin communication operation are shown below. ? external interrupt (intp0); wakeup signal detection use: detects the wakeup signal edges and detects start of communication. ? 16-bit timer/event counter 00 (ti000); baud rate error detection use: detects the baud rate error (measures the ti000 input edge interval in the capture mode) by detecting the tuning break field (sbf) length and divides it by the number of bits. ? serial interface uart6
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 305 15.2 configuration of serial interface uart6 serial interface uart6 consists of the following hardware. table 15-1. configuration of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface transmission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6)
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 306 asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/p13 intst6 asynchronous serial interface control register 6 (asicl6) receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/p14 intsr6 intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) f x -f x /2 10 clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) to50/ti50/p17 (tm50 output) registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit figure 15-4. block diagram of serial interface uart6
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 307 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data converted by the receive shift register. each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the receive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation instruction. no data can be written to this register. reset input sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. transmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset input sets this register to ffh. cautions 1. do not write data to txb6 when bit 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). however, if the same value is continuously transmitted in the transmission mode (power6 = 1 and txe6 = 1), the same value can be written. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first transmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. data is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the internal clock. txs6 cannot be directly manipulated by a program.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 308 15.3 registers controlling serial interface uart6 serial interface uart6 is controlled by the following six registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface reception error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) (1) asynchronous serial interface operation mode register 6 (asim6) this 8-bit register controls the serial transfer operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-5. format of asynchronous serial interface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. caution at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 309 figure 15-5. format of asynchronous serial interface operation mode register 6 (asim6) (2/2) rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception ps61 ps60 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurrence of reception completion interrupt in case of error 0 ? intsre6 ? occurs in case of error (at this time, intsr6 does not occur). 1 ? intsr6 ? occurs in case of error (at this time, intsre6 does not occur). note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0. 2. clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. 3. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 4. make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 5. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 310 (2) asynchronous serial interface reception error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. figure 15-6. format of asynchronous serial interface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol76543210 asis600000pe6fe6ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 311 (3) asynchronous serial interface transmission status register 6 (asif6) this register indicates the status of transmission by serial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register can be set by an 8-bit memory manipulation instruction, and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. figure 15-7. format of asynchronous serial interface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol76543210 asif6000000txbf6txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is transferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer register 6 (txb6) (if data transmission is in progress) cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is complete. data of 2 bytes can be written. when doing so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 312 (4) clock selection register 6 (cksr6) this register selects the base clock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol76543210 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk ) 0000f x (10 mhz) 0001f x /2 (5 mhz) 0010f x /2 2 (2.5 mhz) 0011f x /2 3 (1.25 mhz) 0100f x /2 4 (625 khz) 0101f x /2 5 (312.5 khz) 0110f x /2 6 (156.25 khz) 0111f x /2 7 (78.13 khz) 1000f x /2 8 (39.06 khz) 1001f x /2 9 (19.53 khz) 1010f x /2 10 (9.77 khz) 1 0 1 1 tm50 output (to50) other setting prohibited caution make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 313 (5) baud rate generator control register 6 (brgc6) this register selects the base clock of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-9. format of baud rate generator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol76543210 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 00000 setting prohibited 000010008f xclk /8 000010019f xclk /9 0000101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11111100252f xclk /252 11111101253f xclk /253 11111110254f xclk /254 11111111255f xclk /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clock of the 8-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don't care
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 314 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial transfer operations of serial interface uart6. asicl6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. reset input sets this register to16h. remark asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). however, transfer is started by refresh because bit 6 (sbrt6) and bit 5 (sbtt6) of asicl6 are cleared to 0 when communication is complete (when an interrupt signal is generated). figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff58h after reset: 16h r/w symbol76543210 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger cautions 1. in the case of an sbf reception error, return the mode to the sbf reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 315 figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bits length. 1 1 0 sbf is output with 14-bits length. 1 1 1 sbf is output with 15-bits length. 0 0 0 sbf is output with 16-bits length. 0 0 1 sbf is output with 17-bits length. 0 1 0 sbf is output with 18-bits length. 0 1 1 sbf is output with 19-bits length. 1 0 0 sbf is output with 20-bits length. dir6 msb/lsb-first transfer 0 msb-first transfer 1 lsb-first transfer txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 caution before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 316 15.4 operation of serial interface uart6 this section explains the two modes of serial interface uart6. 15.4.1 operation stop mode in this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. in addition, the pins can be used as ordinary port pins in this mode. (1) register setting the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock. txe6 enables/disables transmission 0 disables transmission operation (synchronously resets the transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0. 2. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 317 15.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) register setting the uart mode is set by asynchronous serial interface operation mode register 6 (asim6), asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), clock selection register 6 (cksr6), baud rate generator control register 6 (brgc6), and asynchronous serial interface control register 6 (asicl6). (a) asynchronous serial interface operation mode register 6 (asim6) this 8-bit register controls the serial transfer operations of serial interface uart6. asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock. txe6 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. caution at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 318 rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception ps61 ps60 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurrence of reception completion interrupt in case of error 0 ? intsre6 ? occurs in case of error (at this time, intsr6 does not occur). 1 ? intsr6 ? occurs in case of error (at this time, intsre6 does not occur). note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0. 2. clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. 3. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 4. make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 5. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 319 (b) asynchronous serial interface reception error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. address: ff53h after reset: 00h r symbol76543210 asis600000pe6fe6ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, refer to chapter 32 cautions for wait.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 320 (c) asynchronous serial interface transmission status register 6 (asif6) this register indicates the status of transmission by serial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register can be set by an 8-bit memory manipulation instruction, and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. address: ff55h after reset: 00h r symbol76543210 asif6000000txbf6txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is transferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer register 6 (txb6) (if data transmission is in progress) cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is complete. data of 2 bytes can be written. when doing so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 321 (d) asynchronous serial interface control register 6 (asicl6) this register controls the serial transfer operations of serial interface uart6. asicl6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. reset input sets this register to16h. remark asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). however, transfer is started by refresh because bit 6 (sbrt6) and bit 5 (sbtt6) of asicl6 are cleared to 0 when communication is complete (when an interrupt signal is generated). address: ff58h after reset: 16h r/w symbol76543210 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger cautions 1. in the case of an sbf reception error, return the mode to the sbf reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 322 sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 msb/lsb-first transfer 0 msb-first transfer 1 lsb-first transfer txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 caution before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 323 (2) communication operation (a) normal transmit/receive data format figure 15-11 shows the format of the transmit/receive data. figure 15-11. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 6 (asim6). whether data is transferred with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is specified by bit 0 (txdlv6) of asicl6.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 324 figure 15-12. example of normal uart transmit/receive data format 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, transfer data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: odd parity, stop bit: 2 bits, transfer data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, transfer data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 325 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 when the device is incorporated in lin. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ? 1 ? : 1 if transmit data has an even number of bits that are ? 1 ? : 0 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ? 1 ? is odd. if transmit data has an odd number of bits that are ? 1 ? : 0 if transmit data has an even number of bits that are ? 1 ? : 1 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ? 0 ? or ? 1 ? . (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 326 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to transmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit shift register 6 (txs6). after that, the data is sequentially output from txs6 to the t x d6 pin, starting from the lsb. when transmission is completed, a transmission completion interrupt request (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 15-13 shows the timing of the transmission completion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 15-13. normal transmission completion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 327 (d) continuous transmission when transmit shift register 6 (txs6) has started the shift operation, the next transmit data can be written to transmit buffer register 6 (txb6). as a result, data can be transmitted without intermission even while an interrupt that has occurred after transmission of one data frame is being serviced, thus realizing an efficient communication rate. to transmit data continuously, however, transmission processing must be executed while referencing bits 1 (txbf6) and 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6). caution when the device is incorporated in lin, the continuous transmission function cannot be used. make sure that asynchronous serial interface transmission status register 6 (asif6) is 00h before writing transmit data to transmit buffer register 6 (txb6). table 15-2. write processing and writing to txb6 during execution of continuous transmission txbf6 txsf6 write processing during execution of continuous transmission writing to txb6 during execution of continuous transmission 0 0 enables writing 2 bytes or transmission completion processing enables writing 0 1 enables writing 1 byte enables writing 1 0 enables writing 2 bytes or transmission completion processing disables writing 1 1 enables writing 1 byte disables writing cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is completed. data of 2 bytes can be written. to do so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 328 figure 15-14 shows the processing flow of continuous transmission. figure 15-14. processing flow of continuous transmission set registers. interrupt occurs. wait for interrupt. transfer executed necessary number of times? write transmit data to txb6 register. write transmit data to txb6 register. read asif6 register. txbf6 = 0? read asif6 register. txsf6 = 1? read asif6 register. txsf6 = 0? no no no no yes yes yes yes completion of transmission processing remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (transmit shift register data flag)
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 329 figure 15-15 shows the timing of starting continuous transmission, and figure 15-16 shows the timing of ending continuous transmission. figure 15-15. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which txbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 330 figure 15-16. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface mode register (asim6) txe6: bit 6 of asynchronous serial interface mode register (asim6)
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 331 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator starts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 15-17). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (rxs6) at the set baud rate. when the stop bit has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receive data is not written to rxb6. even if a parity error (pe6) or a framing error (fe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6/intsre6) is generated on completion of reception. figure 15-17. reception completion interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb6 cautions 1. be sure to read receive buffer register 6 (rxb6) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1 ? . the second stop bit is ignored. 3. be sure to read asynchronous serial interface reception error status register 6 (asis6) before reading rxb6.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 332 (f) reception error three types of errors may occur during reception: a parity error, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status register 6 (asis6) is set as a result of data reception, a reception error interrupt request (intsr6/intsre6) is generated. which error has occurred during reception can be identified by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (refer to table 15-3 ). the contents of asis6 are reset to 0 when asis6 is read. table 15-3. cause of reception error reception error cause value of asis6 parity error the parity specified for transmission does not match the parity of the receive data. 04h framing error stop bit is not detected. 02h overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). 01h the error interrupt can be separated into intsr6 and intsre6 by clearing bit 0 (isrm6) of asynchronous serial interface mode register 6 (asim6) to 0. figure 15-18. reception error interrupt 1. if isrm6 is cleared to 0 (intsr6 and intsre6 are separated) (a) no error during reception (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during reception (b) error during reception intsre6 intsr6 intsre6 intsr6
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 333 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 15-19, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 15-19. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in lin, the sbf (synchronous break field) transmission control function is used for transmission. for the transmission operation of lin, refer to figure 15-1 lin transmission operation . the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1. transmission is enabled when bit 6 (txe6) of asim6 is set to 1 next time, and sbf transmission operation is started when bit 5 (sbtt6) of asynchronous serial interface control register 6 (asicl6) is set to 1. after transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) are output. when sbf transmission has been completed, a transmission completion interrupt request (intst6) is generated, and sbtt6 is automatically cleared. after sbf transmission has been completed, the normal transmission mode is restored. transmission is stopped until the data to be transmitted next is written to transmit buffer register 6 (txb6) or sbtt6 is set to 1. figure 15-20. sbf transmission t x d6 intst6 sbtt6 12 34 56 78910111213stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6)
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 334 (i) sbf reception when the device is incorporated in lin, the sbf (synchronous break field) reception control function is used for reception. for the reception operation of lin, refer to figure 15-2 lin reception operation . reception is enabled when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. when the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt request (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatically cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 15-21. sbf reception 1. normal sbf reception (stop bit is detected with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detected with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ? 0 ? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 335 15.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of baud rate generator ? base clock (clock) the clock selected by bits 3 to 0 (tps63 to tps60) of clock selection register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is 1. this clock is called the base clock (clock) and its frequency is called f xclk . clock is fixed to the low level when power6 = 0. ? transmission counter this counter stops, cleared to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. if there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, cleared to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected.
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 336 figure 15-22. configuration of baud rate generator clock (f xclk ) selector power6 8-bit counter match detector baud rate brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 to50/ti50/p17 (tm50 output) remark power6: bit 7 of asynchronous serial interface mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 337 (2) generation of serial clock a serial clock can be generated by using clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) clock selection register 6 (cksr6) this register selects the base clock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff56h after reset: 00h r/w symbol76543210 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk ) 0000f x (10 mhz) 0001f x /2 (5 mhz) 0010f x /2 2 (2.5 mhz) 0011f x /2 3 (1.25 mhz) 0100f x /2 4 (625 khz) 0101f x /2 5 (312.5 khz) 0110f x /2 6 (156.25 khz) 0111f x /2 7 (78.13 khz) 1000f x /2 8 (39.06 khz) 1001f x /2 9 (19.53 khz) 1010f x /2 10 (9.77 khz) 1 0 1 1 tm50 output other setting prohibited caution make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 338 (b) baud rate generator control register 6 (brgc6) this register selects the base clock of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff57h after reset: ffh r/w symbol76543210 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 00000 setting prohibited 000010008f xclk /8 000010019f xclk /9 0000101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11111100252f xclk /252 11111101253f xclk /253 11111110254f xclk /254 11111111255f xclk /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clock of the 8-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don't care
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 339 (c) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock (clock) selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of brgc6 register (k = 8, 9, 10, ..., 255) (d) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock (clock) = 20 mhz = 20,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 01000001b (k = 65) target baud rate = 153600 bps baud rate = 20 m/(2 65) = 20000000/(2 65) = 153,846 [bps] error = (153846/153600 ? 1) 100 = 0.160 [%] f xclk 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 340 (3) example of setting baud rate table 15-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 101 10371 0.28 1h 101 10475 ? 0.28 19200 1h 130 19231 0.16 1h 109 19200 0.11 0h 109 19220 0.11 31250 1h 80 31250 0.00 0h 134 31268 0.06 0h 67 31268 0.06 38400 0h 130 38462 0.16 0h 109 38440 0.11 0h 55 38090 ? 0.80 76800 0h 65 76923 0.16 0h 55 76182 ? 0.80 0h 27 77593 1.03 115200 0h 43 116279 0.94 0h 36 116388 1.03 0h 18 116389 1.03 153600 0h 33 151515 ? 1.36 0h 27 155185 1.03 0h 14 149643 ? 2.58 230400 0h 22 227272 ? 1.36 0h 18 232777 1.03 0h 9 232778 1.03 caution the maximum permissible frequency (f xclk ) of the base clock is 25 mhz. remark tps63 to tps60: bits 3 to 0 of clock selection register 6 (cksr6) (setting of base clock (f xclk )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f x : x1 input clock oscillation frequency err: baud rate error
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 341 (4) permissible baud rate range during reception the permissible error from the baud rate at the transmission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 15-23. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax transfer rate of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible transfer rate maximum permissible transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-23, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (brgc6) after the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks minimum permissible transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 342 therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible transfer rate can be calculated as follows. 10 k + 2 21k ? 2 11 2 k2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 15-5. maximum/minimum permissible baud rate error division ratio (k) maximum permissible baud rate error minimum permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2
chapter 15 serial interface uart6 preliminary user ? s manual u15947ej1v1ud 343 (5) transfer rate during continuous transmission when data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two clocks from the normal value. however, the result of transfer is not affected because the timing is initialized on the reception side when the start bit is detected. figure 15-24. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk , the following expression is satisfied. flstp = fl + 2/f xclk therefore, the transfer rate during continuous transmission is: transfer rate = 11 fl + 2/f xclk
preliminary user?s manual u15947ej1v1ud 344 chapter 16 serial interfaces csi10 and csi11 the pd780143 and 780144 incorporate serial interface csi10, and the pd780146, 780148, and 78f0148 incorporate serial interfaces csi10 and csi11. 16.1 functions of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 note have the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial i/o mode (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock line (sck1n) and two serial data lines (si1n and so1n). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is useful for connecting peripheral i/os and display controllers with a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. note pd780146, 780148, and 78f0148 only 16.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 consist of the following hardware. table 16-1. configuration of serial interfaces csi10 and csi11 item configuration registers transmit buffer register 1n (sotb1n) serial i/o shift register 1n (sio1n) control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u15947ej1v1ud 345 figure 16-1. block diagram of serial interface csi10 8 8 so10/p12 intcsi10 si10/p11/r x d0 output selector f x /2 to f x /2 7 sck10/p10/t x d0 internal bus serial i/o shift register 10 (sio10) transmit buffer register 10 (sotb10) output latch transmit controller clock start/stop controller & clock phase controller selector transmit data controller figure 16-2. block diagram of serial interface csi11 ( pd780146, 780148, and 78f0148 only) 8 8 so11/p02 intcsi11 si11/p03 output selector f x /2 to f x /2 7 sck11/p04 ssi11/p05/ti001 internal bus serial i/o shift register 11 (sio11) transmit buffer register 11 (sotb11) output latch transmit controller clock start/stop controller & clock phase controller selector transmit data controller
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 346 (1) transmit buffer register 1n (sotb1n) this register sets the transmit data. transmission/reception is started by writing data to sotb1n when bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. the data written to sotb1n is converted from parallel data into serial data by serial i/o shift register 1n, and output to the serial output pin (so1n). sotb1n can be written or read by an 8-bit memory manipulation instruction. reset input makes this register undefined. caution do not access sotb1n when csot1n = 1 (during serial communication). remarks 1. when using serial interface csi11 in the slave mode, the operation is as follows if bit 5 (sse11) of serial operation mode register 11 (csim11) is 1. (1) if ssi11 is low ... this chip is selected and transmission is started by writing data to sotb11. (2) if ssi11 is high ... transmission is not started even if data is written to sotb11 because this chip is not selected (transmission held pending). (3) if data is written to sotb11 when transmission is held pending because ssi11 is high and then ssi11 goes low ... transmission is started. (4) if ssi11 goes high after transmission has been started by writing data to sotb11 when ssi11 is low ... transmission is aborted. 2. n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user?s manual u15947ej1v1ud 347 (2) serial i/o shift register 1n (sio1n) this is an 8-bit register that converts data from parallel data into serial data and vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data from sio1n if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 0. during reception, the data is read from the serial input pin (si1n) to sio1n. reset input clears this register to 00h. caution do not access sio1n when csot1n = 1 (during serial communication). remark when using serial interface csi11 in the slave mode, the operation is as follows if bit 5 (sse11) of serial operation mode register 11 (csim11) is 1. (1) if ssi11 is low ... this chip is selected and reception is started by reading data from sio11. (2) if ssi11 is high ... reception is not started even if data is read from sio11 because this chip is not selected (reception held pending). (3) if data is read from sio11 when reception is held pending because ssi11 is high and then ssi11 goes low ... reception is started. (4) if ssi11 goes high after reception has been started by reading data from sio11 when ssi11 is low ... reception is aborted. 16.3 registers controlling serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 are controlled by the following two registers. ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) (1) serial operation mode register 1n (csim1n) csim1n is used to select the operation mode and enable or disable operation. csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 348 figure 16-3. format of serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins can be used as general- purpose port pins). 1 enables operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins are at active level). trmd10 note 2 transmit/receive mode control 0 note 3 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 4 first bit specification 0msb 1lsb csot10 note 5 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. do not rewrite trmd10 when csot10 = 1 (during serial communication). 3. the so10 pin is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 4. do not rewrite dir10 when csot10 = 1 (during serial communication). 5. csot10 is cleared if csie10 is set to 0 (operation stopped). caution be sure to set bit 5 to 0.
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 349 figure 16-4. format of serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol76543210 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 stops operation (si11/p03, so11/p02, and sck11/p04 pins can be used as general-purpose port pins). 1 enables operation (si11/p03, so11/p02, and sck11/p04 pins are at active level). trmd11 note 2 transmit/receive mode control 0 note 3 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 4, 5 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 6 first bit specification 0msb 1lsb csot11 note 7 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. do not rewrite trmd11 when csot11 = 1 (during serial communication). 3. the so11 pin is fixed to the low level when trmd11 is 0. reception is started when data is read from sio11. 4. do not rewrite sse11 when csot11 = 1 (during serial communication). 5. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 6. do not rewrite dir11 when csot11 = 1 (during serial communication). 7. csot11 is cleared if csie11 is set to 0 (operation stopped).
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 350 (2) serial clock selection register 1n (csic1n) csic1n is used to select the phase of the data clock and set the count clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 figure 16-5. format of serial clock selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol76543210 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock input to sck10 cautions 1. do not write csic10 during a communication operation or when using p10/sck10/t x d0, p11/si10/r x d0, and p12/so10 as general-purpose port pins. 2. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 351 figure 16-6. format of serial clock selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol76543210 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 cks112 cks111 cks110 csi11 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock input to sck11 cautions 1. do not write csic11 during a communication operation or when using p02/so11, p03/si11, and p04/sck11 as general-purpose port pins. 2. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 352 16.4 operation of serial interfaces csi10 and csi11 serial interface csi10 and csi11 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 16.4.1 operation stop mode serial transfer is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10/t x d0, p11/si10/r x d0, p12/so10, p02/so11 note , p03/si11 note , and p04/sck11 note pins can be used as ordinary i/o port pins in this mode. note pd780146, 780148, and 78f0148 only (1) register setting the operation stop mode is set by serial operation mode register 1n (csim1n). (a) serial operation mode register 1n (csim1n) csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1n to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins can be used as general- purpose port pins). 1 enables operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins are at active level). ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w symbol76543210 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 stops operation (si11/p03, so11/p02, and sck11/p04 pins can be used as general-purpose port pins). 1 enables operation (si11/p03, so11/p02, and sck11/p04 pins are at active level).
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 353 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connecting peripheral i/os and display controllers that have a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. in this mode, communication is executed by using three lines: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) register setting the 3-wire serial i/o mode is set by serial operation mode register 1n (csim1n) and serial clock selection register 1n (csic1n). (a) serial operation mode register 1n (csim1n) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 354 ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins can be used as general- purpose port pins). 1 enables operation (si10/p11/r x d0, so10/p12, and sck10/p10/t x d0 pins are at active level). trmd10 note 2 transmit/receive mode control 0 note 3 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 4 first bit specification 0msb 1lsb csot10 note 5 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. do not rewrite trmd10 when csot10 = 1 (during serial communication). 3. the so10 pin is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 4. do not rewrite dir10 when csot10 = 1 (during serial communication). 5. csot10 is cleared if csie10 is set to 0 (operation stopped). caution be sure to set bit 5 to 0.
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 355 ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol76543210 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 stops operation (si11/p03, so11/p02, and sck11/p04 pins can be used as general-purpose port pins). 1 enables operation (si11/p03, so11/p02, and sck11/p04 pins are at active level). trmd11 note 2 transmit/receive mode control 0 note 3 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 4, 5 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 6 first bit specification 0msb 1lsb csot11 note 7 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. do not rewrite trmd11 when csot11 = 1 (during serial communication). 3. the so11 pin is fixed to the low level when trmd11 is 0. reception is started when data is read from sio11. 4. do not rewrite sse11 when csot11 = 1 (during serial communication). 5. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 6. do not rewrite dir11 when csot11 = 1 (during serial communication). 7. csot11 is cleared if csie11 is set to 0 (operation stopped).
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 356 (b) serial clock selection register 1n (csic1n) csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148 ? serial clock selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol76543210 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock input to sck10 cautions 1. do not write csic10 during a communication operation or when using p10/sck10/t x d0, p11/si10/r x d0, and p12/so10 as general-purpose port pins. 2. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 357 ? serial clock selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol76543210 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 cks112 cks111 cks110 csi11 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock input to sck11 cautions 1. do not write csic11 during a communication operation or when using p02/so11, p03/si11, and p04/sck11 as general-purpose port pins. 2. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 358 (2) setting of ports ? ? ? ? serial interface csi10 <1> transmit/receive mode (a) to use externally input clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 2 (pm12) of port mode register 1: cleared to 0 bit 0 (pm10) of port mode register 1: set to 1 bit 2 (p12) of port 1: cleared to 0 (b) to use internal clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 2 (pm12) of port mode register 1: cleared to 0 bit 0 (pm10) of port mode register 1: cleared to 0 bit 2 (p12) of port 1: cleared to 0 bit 0 (p10) of port 1: set to 1 <2> receive mode (with transmission disabled) (a) to use externally input clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 0 (pm10) of port mode register 1: set to 1 (b) to use internal clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 0 (pm10) of port mode register 1: cleared to 0 bit 0 (p10) of port 1: set to 1 remark the transmit/receive mode or receive mode is selected by using bit 6 (trmd10) of serial operation mode register 10 (csim10).
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 359 ? ? ? ? serial interface csi11 <1> transmit/receive mode (a) to use externally input clock as system clock (sck11) bit 3 (pm03) of port mode register 0: set to 1 bit 2 (pm02) of port mode register 0: cleared to 0 bit 4 (pm04) of port mode register 0: set to 1 bit 2 (p02) of port 0: cleared to 0 (b) to use internal clock as system clock (sck11) bit 3 (pm03) of port mode register 0: set to 1 bit 2 (pm02) of port mode register 0: cleared to 0 bit 4 (pm04) of port mode register 0: cleared to 0 bit 2 (p02) of port 0: cleared to 0 bit 4 (p04) of port 0: set to 1 <2> receive mode (with transmission disabled) (a) to use externally input clock as system clock (sck11) bit 3 (pm03) of port mode register 0: set to 1 bit 4 (pm04) of port mode register 0: set to 1 (b) to use internal clock as system clock (sck11) bit 3 (pm03) of port mode register 0: set to 1 bit 4 (pm04) of port mode register 0: cleared to 0 bit 4 (p04) of port 0: set to 1 remark the transmit/receive mode or receive mode is selected by using bit 6 (trmd11) of serial operation mode register 11 (csim11).
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 360 (3) communication operation in the 3-wire serial i/o mode, data is transmitted or received in 8-bit units. each bit of the data is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is written to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 0. reception is started when data is read from serial i/o shift register 1n (sio1n). when using serial interface csi11, however, the communication operation is not started if bit 5 (sse11) of csim11 is 1 in the slave mode, and the ssi11 pin is at the high level. after communication has been started, bit 0 (csot1n) of csim1n is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1n) is set, and csot1n is cleared to 0. then the next communication is enabled. cautions 1. do not access the control register and data register when csot1n = 1 (during serial communication). 2. when using serial interface csi11, wait for the duration of at least one clock before the clock operation is started to change the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. remark n = 0, 1
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 361 figure 16-7. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception timing (type 1; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 362 figure 16-7. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception timing (type 2; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 363 figure 16-8. timing of clock/data phase (a) type 1; ckp1n = 0, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2; ckp1n = 0, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3; ckp1n = 1, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4; ckp1n = 1, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 364 (4) timing of output to so1n pin (first bit) when communication is started, the value of transmit buffer register 1n (sotb1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 16-9. output operation of first bit (1) when ckp1n = 0, dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch the first bit is directly latched by the sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transferred to the sio1n register at the next rising (or falling) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latched by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. (2) when ckp1n = 0, dap1n = 1 (or ckp1n = 1, dap1n = 1) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch the first bit is directly latched by the sotb1n register at the falling edge of the write signal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transferred to the sio1n register at the next falling (or rising) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latched by the sio1n register to the output latch at the next rising (or fa lling) edge of sck1n, and the data is output from the so1n pin. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 365 (5) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 16-10. output value of so1n pin (last bit) (1) type 1; when ckp1n = 0 and dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n ( next request is issued.) last bit output latch (2) type 2; when ckp1n = 0 and dap1n = 1 (or ckp1n = 1, dap1n = 1) sck1n sotb1n sio1n so1n last bit writing to sotb1n or reading from sio1n ( next request is issued.) output latch remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 16 serial interfaces csi10 and csi11 preliminary user ? s manual u15947ej1v1ud 366 (6) so1n pin the status of the so1n pin is as follows if bit 7 (csie1n) of serial operation mode register 1n (csim1n) is cleared to 0. table 16-2. so1n pin status trmd1n dap1n dir1n so1n pin trmd1n = 0 note ?? outputs low level note . dap1n = 0 ? value of so1n latch (low-level output) dir1n = 0 value of bit 7 of sotb1n trmd1n = 1 dap1n = 1 dir1n = 1 value of bit 0 of sotb1n note status after reset caution if a value is written to trmd1n, dap1n, and dir1n, the output value of the so1n pin changes. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
preliminary user?s manual u15947ej1v1ud 367 chapter 17 serial interface csia0 17.1 functions of serial interface csia0 serial interface csia0 has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial i/o mode (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock line (scka0) and two serial data lines (sia0 and soa0). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. (3) 3-wire serial i/o mode with automatic transmit/receive function (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock line (scka0) and two serial data lines (sia0 and soa0). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. data can be transferred to/from a display driver etc. without using software since a 32-byte transfer buffer ram is incorporated. also, the incorporation of handshake pins (stb0, busy0) has made connection to peripheral lsis easy. ? master mode/slave mode selectable ? transfer data length: 8 bits ? msb/lsb-first selectable for transfer data ? automatic transmit/receive function: number of transfer bytes can be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single transfer/repeat transfer selectable ? on-chip dedicated baud rate generator (6/8/16/32 divisions) ? 3-wire soa0: serial data output sia0: serial data input scka0: serial clock i/o ? handshake function incorporated stb0: strobe output busy0: busy input ? transmission/reception completion interrupt: intacsi ? internal 32-byte buffer ram
chapter 17 serial interface csia0 preliminary user?s manual u15947ej1v1ud 368 17.2 configuration of serial interface csia0 serial interface csia0 consists of the following hardware. table 17-1. configuration of serial interface csia0 item configuration register serial i/o shift register 0 (sioa0) automatic data transfer address count register 0 (adtc0) control registers serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0)
chapter 17 serial interface csia0 preliminary user?s manual u15947ej1v1ud 369 figure 17-1. block diagram of serial interface csia0 internal bus selector f x /6 to f x /32 selector master0 p145 p142 pm142 pm145 pm144 scka0/p142 busy0/p141 stb0/p145 soa0/p144 sia0/p143 dir0 ate0 6-bit counter buffer ram interrupt generator serial transfer controller atm0 serial clock counter stbe0 busye0 atstp0 atsta0 busylv0 erre0 errf0 tsf0 automatic data transfer address point specification register 0 (adtp0) automatic data transfer address count register 0 (adtc0) divisor selection register 0 (brgca0) serial i/o shift register 0 (sioa0) automatic data transfer interval specification register 0 (adti0) intacsi rxae txae p144 3 4 2 serial trigger register 0 (csit0) serial status register 0 (csis0) f x
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 370 (1) serial i/o shift register 0 (sioa0) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 0). writing transmit data to sioa0 starts the transfer. in addition, after a transfer completion interrupt request (intacsi) is output (bit 0 (tsf0) of serial status register 0 (csis0) = 0), data can be received by reading data from sioa0. this register can be written or read by an 8-bit memory manipulation instruction. however, writing to sioa0 is prohibited when bit 0 (tsf0) of serial status register 0 (csis0) = 1 reset input sets this register 00h. cautions 1. a transfer operation is started by writing to sioa0. consequently, when transmission is disabled (bit 3 (txea0) of csima0 = 0), write dummy data to the sioa0 register to start the transfer operation, and then perform a receive operation. 2. do not write data to sioa0 while the automatic transmit/receive function is operating. (2) automatic data transfer address count register 0 (adtc0) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtc0 register value. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 00h. however, reading from adtc0 is prohibited when bit 0 (tsf0) of serial status register 0 (csis0) = 1. figure 17-2. format of automatic data transfer address count register 0 (adtc0) 0 adtc0 0 0 adtc04 adtc03 adtc02 adtc01 adtp00 address: ff97h after reset: 00h r symbol 43 21 0 6 75 17.3 registers controlling serial interface csia0 serial interface csia0 is controlled by the following six registers. ? serial operation mode specification register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) (1) serial operation mode specification register 0 (csima0) this is an 8-bit register used to control the serial transfer operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 371 figure 17-3. format of serial operation mode specification register 0 (csima0) csiae0 csia0 operation disabled (soa0: low level, scka0: high level) csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte transfer mode automatic transfer mode ate0 0 1 control of automatic transfer operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic transfer mode specification slave mode (synchronous with scka0 input clock) master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, all the registers of the csia0 unit are initialized asynchronously. to set csiae0 = 1 again, be sure to re-set the registers of the csia0 unit. 3. when csiae0 is re-set to 1 after csiae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 372 (2) serial status register 0 (csis0) this is an 8-bit register used to select the input clock and to control the transfer operation of csia0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting csis0 is prohibited when bit 0 (tsf0). figure 17-4. format of serial status register 0 (csis0) (1/2) 0 csis0 symbol 0 stbe0 busye0 busylv0 erre0 errf0 tsf0 strobe output disabled strobe output enabled stbe0 notes 2, 3 0 1 strobe output enable/disable busy signal detection disabled (input via busy0 pin is ignored) busy signal detection enabled and transfer wait by busy signal is executed busye0 0 1 busy signal detection enable/disable low level high level busylv0 note 4 0 1 busy signal active level setting address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 notes 1. bits 0 and 1 are read-only. 2. stbe0 is valid only in master mode. in slave mode, 1-byte transfer ends after eight transfer clocks regardless of the stbe0 set value. 3. when stbe0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (adti0). that is, 10 transfer clocks are used for 1-byte transfer even if adti0 = 00h is set. 4. in bit error detection by busy input, the active level specified by busylv0 is detected. caution be sure to set bits 6 and 7 to 0.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 373 figure 17-4. format of serial status register 0 (csis0) (2/2) error detection disabled error detection enabled erre0 note 0 1 bit error detection enable/disable bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input when transfer is started by setting bit 0 (atsta0) of serial trigger register 0 (csit0) to 1 or writing to sioa0. bit error detected (when erre0 = 1, the level specified by busylv0 during the data bit transfer period is detected via busy0 pin input). errf0 0 1 bit error detection flag bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input at the end of the specified transfer when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag note the erre0 setting is valid even when busye0 = 0. caution when tsf0 is 1, rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0), divisor selection register 0 (brgca0), automatic data transfer address point specification register 0 (adtp0), automatic data transfer interval specification register 0 (adti0), and serial i/o shift register 0 (sioa0) are prohibited. however, these registers can be read and re-written to the same value. in addition, the buffer ram can be rewritten during transfer.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 374 (3) serial trigger register 0 (csit0) this is an 8-bit register used to control execution/stop of automatic data transfer. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, manipulate only when bit 6 (ate0) of serial operation mode specification register 0 (csima0) is 1 (manipulation prohibited when ate0 = 0). figure 17-5. format of serial trigger register 0 (csit0) 0 csit0 symbol 0 0 0 0 0 atstp0 atsta0 normal mode automatic data transfer stopped atstp0 0 1 automatic data transfer stop normal mode automatic data transfer started atsta0 0 1 automatic data transfer start address: ff92h after reset: 00h r/w 43 21 0 6 75 cautions 1. even if atstp0 or atsta0 is set to 1, automatic transfer cannot be started/stopped until 1- byte transfer is complete. 2. atstp0 and atsta0 retain 1 until immediately before the interrupt signal intacsi is generated, and then change to 0 automatically. 3. after automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (adtc0). however, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting atstp0 = 1, start automatic data transfer by atsta0 after re-setting the registers.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 375 (4) divisor selection register 0 (brgca0) this is an 8-bit register used to control the serial transfer speed (divisor of csia input clock). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. figure 17-6. format of divisor selection register 0 (brgca0) 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 csia0 input clock (f w ) division ratio selection f w /6 (1.67 mhz) f w /2 3 (1.25 mhz) f w /2 4 (625 khz) f w /2 5 (312.5 khz) address: ff93h after reset: 03h r/w 43 21 0 6 75 remark figures in parentheses apply to operation with f w = 10 mhz, f w = f x (x1 input clock oscillation frequency). (5) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffer ram address that ends transfer during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 = 1). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adtp0 is prohibited. in the 78k0/kf1 series, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when adtp0 is set to 07h 8 bytes of 00h to 07h are transferred. in repeat transfer mode (bit 5 (atm0) of csima0 = 1), transfer is performed repeatedly up to the address value set in adtp0. example when 07h is transferred to adtp0 (repeat transfer mode) transfer is repeated as 00h to 07h, 00h to 07h, ? . figure 17-7. format of automatic data transfer address point specification register 0 (adtp0) 0 adtp0 0 0 adtp04 adtp03 adtp02 adtp01 adtp00 address: ff94h after reset: 00h r/w symbol 43 21 0 6 75 caution be sure to set bits 7 to 5 to 0.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 376 the relationship between buffer ram address values and adtp0 setting values is shown below. table 17-2. relationship between buffer ram address values and adtp0 setting values buffer ram address value adtp0 setting value buffer ram address value adtp0 setting value fa00h 00h fa10h 10h fa01h 01h fa11h 11h fa02h 02h fa12h 12h fa03h 03h fa13h 13h fa04h 04h fa14h 14h fa05h 05h fa15h 15h fa06h 06h fa16h 16h fa07h 07h fa17h 17h fa08h 08h fa18h 18h fa09h 09h fa19h 19h fa0ah 0ah fa1ah 1ah fa0bh 0bh fa1bh 1bh fa0ch 0ch fa1ch 1ch fa0dh 0dh fa1dh 1dh fa0eh 0eh fa1eh 1eh fa0fh 0fh fa1fh 1fh
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 377 (6) automatic data transfer interval specification register 0 (adti0) this is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 1). set this register when in master mode (bit 4 (master0) of csima0 = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (bit 6 (ate0) of csima0 = 0) is also valid. when the interval time specified by adti0 after the end of 1-byte transfer has elapsed, an interrupt request signal (intacsi) is output. the number of clocks for the interval can be set to between 0 and 63 clocks. the specified interval time is the transfer clock (specified by divisor selection register 0 (brgca0)) multiplied by an integer value. example when adti0 = 03h scka0 interval time of 3 clocks this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adti0 is prohibited. figure 17-8. format of automatic data transfer interval specification register 0 (adti0) 0 adti0 0 adti05 adti04 adti03 adti02 adti01 adti00 address: ff95h after reset: 00h r/w symbol 43 21 0 6 75 caution because the setting of bit 5 (stbe0) and bit 4 (busye0) of serial status register 0 (csis0) takes priority over the adti0 setting, the interval time based on the setting of stbe0 and busye0 is generated even when adti0 is set to 00h. example <1> when stbe = 1, busye = 0: interval time of two transfer clocks is generated <2> when stbe = 0, busye = 1: interval time of one transfer clock is generated <3> when stbe = 1, busye = 1: interval time of two transfer clocks is generated therefore, setting stbe0 and busye0 to 0 is required to perform no-wait transfer.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 378 17.4 operation of serial interface csia0 serial interface csia0 can be used in the following three modes. operation stop mode 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 17.4.1 operation stop mode serial transfer is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p142/scka0, p143/sia0, and p144/soa0 pins can be used as ordinary i/o port pins in this mode. (1) register setting the operation stop mode is set by serial operation mode specification register 0 (csima0). (a) serial operation mode specification register 0 (csima0) this is an 8-bit register used to control the serial transfer operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. csiae0 csia0 operation disabled (soa0: low level, scka0: high level) csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 address: ff90h after reset: 00h r/w 17.4.2 3-wire serial i/o mode the one-byte data transmission/reception is executed in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is set to 0. the 3-wire serial i/o mode is useful for connecting peripheral i/os and display controllers having a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. in this mode, communication is executed by using three lines: serial clock (scka0), serial output (soa0), and serial input (sia0) lines. (1) register setting serial interface csia0 is controlled by the following three registers. serial operation mode specification register 0 (csima0) serial status register 0 (csis0) divisor selection register 0 (brgca0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 379 (a) serial operation mode specification register 0 (csima0) this is an 8-bit register used to control the serial transfer operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. csiae0 csia0 operation disabled (soa0: low level, scka0: high level) csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte transfer mode automatic transfer mode ate0 0 1 control of automatic transfer operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic transfer mode specification slave mode (synchronous with scka0 input clock) master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, all the registers of the csia0 unit are initialized asynchronously. to set csiae0 = 1 again, be sure to re-set the registers of the csia0 unit. 3. when csiae0 is re-set to 1 after csiae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 380 (b) serial status register 0 (csis0) this is an 8-bit register used to select the input clock and to control the transfer operation of csia0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting csis0 is prohibited when bit 0 (tsf0) is 1. 0 csis0 symbol 0 stbe0 busye0 busylv0 erre0 errf0 tsf0 strobe output disabled strobe output enabled stbe0 notes 2, 3 0 1 strobe output enable/disable busy signal detection disabled (input via busy0 pin is ignored) busy signal detection enabled and transfer wait by busy signal is executed busye0 0 1 busy signal detection enable/disable low level high level busylv0 note 4 0 1 busy signal active level setting address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 notes 1. bits 0 and 1 are read-only. 2. stbe0 is valid only in master mode. in slave mode, 1-byte transfer ends after eight transfer clocks regardless of the stbe0 set value. 3. when stbe0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (adti0). that is, 10 transfer clocks are used for 1-byte transfer even if adti0 = 00h is set. 4. in bit error detection by busy input, the active level specified by busylv0 is detected. caution be sure to set bits 6 and 7 to 0.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 381 error detection disabled error detection enabled erre0 note 0 1 bit error detection enable/disable bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input when transfer is started by setting bit 0 (atsta0) of serial trigger register 0 (csit0) to 1 or writing to sioa0. bit error detected (when erre0 = 1, the level specified by busylv0 during the data bit transfer period is detected via busy0 pin input). errf0 0 1 bit error detection flag bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input at the end of the specified transfer when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag note the erre0 setting is valid even when busye0 = 0. caution when tsf0 is 1, rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0), divisor selection register 0 (brgca0), automatic data transfer address point specification register 0 (adtp0), automatic data transfer interval specification register 0 (adti0), and serial i/o shift register 0 (sioa0) are prohibited. however, these registers can be read and re-written to the same value. in addition, the buffer ram can be rewritten during transfer.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 382 (c) divisor selection register 0 (brgca0) this is an 8-bit register used to control the serial transfer speed (divisor of csia input clock). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 csia0 input clock (f w ) division ratio selection f w /6 (1.67 mhz) f w /2 3 (1.25 mhz) f w /2 4 (625 khz) f w /2 5 (312.5 khz) address: ff93h after reset: 03h r/w 43 21 0 6 75 remark figures in parentheses apply to operation with f w = 10 mhz, f w = f x (x1 input clock oscillation frequency) the relationship between register settings and pins is shown below. operation enabled scka0 (input) csiae0 0 master0 p143 pm144 p144 pm142 serial i/o shift register 0 operation serial clock counter operation control sia0/p143 pin function scka0/p142 pin function 1 0 0 001 1 count operation sia0 note 2 (input) operation stopped clear p143 (cmos i/o) p142 (cmos i/o) pm143 soa0/p144 pin function soa0 (cmos output) p144 (cmos i/o) scka0 (cmos output) 1 p142 note 1 note 1 note 1 note 1 note 1 1 note 2 note 1 note 2 notes 1. can be used freely as port function. 2. can be used as p143 (cmos i/o) when only transmission is performed (clear bit 2 (rxea0) of csima0 to 0). remark :don ? t care csiae0: bit 7 of serial operation mode specification register 0 (csima0) master0: bit 4 of csima0 pm : port mode register p : port output latch
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 383 (3) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception when bit 7 (csiae0) and bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 1, 0, respectively, if transfer data is written to serial i/o shift register 0 (sioa0), the data is output via the soa0 pin in synchronization with the serial clock falling edge, and then input via the sia0 pin in synchronization with serial clock falling edge, and stored in the sioa0 register in synchronization with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, transfer can only be started by writing a dummy value to the sioa0 register. when transfer of 1 byte is complete, an interrupt request signal (intacsi) is generated. in 1-byte transmission/reception, the setting of bit 5 (atm0) of csima0 is invalid. be sure to read data after confirming that bit 0 (tsf0) of serial status register 0 (csis0) = 0. figure 17-9. 3-wire serial i/o mode timing sia0 scka0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 soa0 do7 do6 do5 do4 do3 do2 do1 do0 acsiif transfer starts at falling edge of scka0 end of transfer sioa0 write caution the soa0 pin becomes low level by an sioa0 write.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 384 (b) data format in the data format, data is changed in synchronization with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-10. format of transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 385 (c) switching msb/lsb as start bit figure 17-11 shows the configuration of serial i/o shift register 0 (sioa0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. switching msb/lsb as the start bit can be specified using bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-11. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sia0 shift register 0 (sioa0) read/write gate soa0 scka0 dq soa0 latch start bit switching is realized by switching the bit order for data written to sioa0. the sioa0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (d) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sioa0) when the following two conditions are satisfied. ? serial interface csia0 operation control bit (csiae0) = 1 ? internal serial clock is stopped or scka0 is high level after 8-bit serial transfer. caution if csiae0 is set to 1 after data is written to sioa0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (acsiif) is set.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 386 17.4.3 3-wire serial i/o mode with automatic transmit/receive function up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is set to 1. after transfer is started, only data of the set number of bytes stored in ram in advance can be transmitted, and only data of the set number of bytes can be received and stored in ram. in addition, to transmit/receive data continuously, handshake signals (stb0 and busy0) generated by hardware are supported. therefore, connection to peripheral lsis such as osd (on screen display) lsis and lcd controller/drivers can be easily realized. (1) register setting serial interface csia0 is controlled by the following six registers. serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 387 (a) serial operation mode specification register 0 (csima0) this is an 8-bit register used to control the serial transfer operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. csiae0 csia0 operation disabled (soa0: low level, scka0: high level) csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte transfer mode automatic transfer mode ate0 0 1 control of automatic transfer operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic transfer mode specification slave mode (synchronous with scka0 input clock) master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, all the registers of the csia0 unit are initialized asynchronously. to set csiae0 = 1 again, be sure to re-set the registers of the csia0 unit. 3. when csiae0 is re-set to 1 after csiae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 388 (b) serial status register 0 (csis0) this is an 8-bit register used to select the input clock and to control the transfer operation of csia0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting csis0 is prohibited when bit 0 (tsf0) is 1. 0 csis0 symbol 0 stbe0 busye0 busylv0 erre0 errf0 tsf0 strobe output disabled strobe output enabled stbe0 notes 2, 3 0 1 strobe output enable/disable busy signal detection disabled (input via busy0 pin is ignored) busy signal detection enabled and transfer wait by busy signal is executed busye0 0 1 busy signal detection enable/disable low level high level busylv0 note 4 0 1 busy signal active level setting address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 notes 1. bits 0 and 1 are read-only. 2. stbe0 is valid only in master mode. in slave mode, 1-byte transfer ends after eight transfer clocks regardless of the stbe0 set value. 3. when stbe0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (adti0). that is, 10 transfer clocks are used for 1-byte transfer even if adti0 = 00h is set. 4. in bit error detection by busy input, the active level specified by busylv0 is detected. caution be sure to set bits 6 and 7 to 0.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 389 error detection disabled error detection enabled erre0 note 0 1 bit error detection enable/disable bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input when transfer is started by setting bit 0 (atsta0) of serial trigger register 0 (csit0) to 1 or writing to sioa0. bit error detected (when erre0 = 1, the level specified by busylv0 during the data bit transfer period is detected via busy0 pin input). errf0 0 1 bit error detection flag bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input at the end of the specified transfer when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag note the erre0 setting is valid even when busye0 = 0. caution when tsf0 is 1, rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0), divisor selection register 0 (brgca0), automatic data transfer address point specification register 0 (adtp0), automatic data transfer interval specification register 0 (adti0), and serial i/o shift register 0 (sioa0) are prohibited. however, these registers can be read and re-written to the same value. in addition, the buffer ram can be rewritten during transfer.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 390 (c) serial trigger register 0 (csit0) this is an 8-bit register used to control execution/stop of automatic data transfer. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, manipulate only when bit 6 (ate0) of serial operation mode specification register 0 (csima0) is 1 (manipulation prohibited when ate0 = 0). 0 csit0 symbol 0 0 0 0 0 atstp0 atsta0 normal mode automatic data transfer stopped atstp0 0 1 automatic data transfer stop normal mode automatic data transfer started atsta0 0 1 automatic data transfer start address: ff92h after reset: 00h r/w 43 21 0 6 75 cautions 1. even if atstp0 or atsta0 is set to 1, automatic transfer cannot be started/stopped until 1- byte transfer is complete. 2. atstp0 and atsta0 retain 1 until immediately before the interrupt signal intacsi is generated, and then change to 0 automatically. 3. after automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (adtc0). however, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting atstp0 = 1, start automatic data transfer by atsta0 after re-setting the registers. (d) divisor selection register 0 (brgca0) this is an 8-bit register used to control the serial transfer speed (divisor of csia input clock). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 csia0 input clock (f w ) division ratio selection f w /6 (1.67 mhz) f w /2 3 (1.25 mhz) f w /2 4 (625 khz) f w /2 5 (312.5 khz) address: ff93h after reset: 03h r/w 43 21 0 6 75 remark figures in parentheses apply to operation with f w = 10 mhz, f w = f x (x1 input clock oscillation frequency)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 391 (e) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffer ram address that ends transfer during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 1). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adtp0 is prohibited. in the 78k0/kf1 series, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when adtp0 is set to 07h 8 bytes of 00h to 07h are transferred. in repeat transfer mode (bit 5 (atm0) of csima0 = 1), transfer is performed repeatedly up to the address value set in adtp0. example when 07h is transferred to adtp0 (repeat transfer mode) transfer is repeated as 00h to 07h, 00h to 07h, ? . 0 adtp0 0 0 adtp04 adtp03 adtp02 adtp01 adtp00 address: ff94h after reset: 00h r/w symbol 43 21 0 6 75 caution be sure to set bits 7 to 5 to 0. the relationship between buffer ram address values and adtp0 setting values is shown below. buffer ram address value adtp0 setting value buffer ram address value adtp0 setting value fa00h 00h fa10h 10h fa01h 01h fa11h 11h fa02h 02h fa12h 12h fa03h 03h fa13h 13h fa04h 04h fa14h 14h fa05h 05h fa15h 15h fa06h 06h fa16h 16h fa07h 07h fa17h 17h fa08h 08h fa18h 18h fa09h 09h fa19h 19h fa0ah 0ah fa1ah 1ah fa0bh 0bh fa1bh 1bh fa0ch 0ch fa1ch 1ch fa0dh 0dh fa1dh 1dh fa0eh 0eh fa1eh 1eh fa0fh 0fh fa1fh 1fh
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 392 (f) automatic data transfer interval specification register 0 (adti0) this is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 1). set this register when in master mode (bit 4 (master0) of csima0 = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (bit 6 (ate0) of csima0 = 0) is also valid. when the interval time specified by adti0 after the end of 1-byte transfer has elapsed, an interrupt request signal (intacsi) is output. the number of clocks for the interval can be set to between 0 an 63 clocks. the specified interval time is the transfer clock (specified by divisor selection register 0 (brgca0)) multiplied by an integer value. example when adti0 = 03h scka0 interval time of 3 clocks this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adti0 is prohibited. 0 adti0 0 adti05 adti04 adti03 adti02 adti01 adti00 address: ff95h after reset: 00h r/w symbol 43 21 0 6 75 caution because the setting of bit 5 (stbe0) and bit 4 (busye0) of serial status register 0 (csis0) takes priority over the adti0 setting, the interval time based on the setting of stbe0 and busye0 is generated even when adti0 is set to 00h. example <1> when stbe = 1, busye = 0: interval time of two transfer clocks is generated <2> when stbe = 0, busye = 1: interval time of one transfer clock is generated <3> when stbe = 1, busye = 1: interval time of two transfer clocks is generated therefore, setting stbe0 and busye0 to 0 is required to perform no-wait transfer.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 393 (3) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fa00h of buffer ram (up to fa1fh at maximum). the transmit data should be in the order from lower address to higher address. <2> set the automatic data transfer address point specification register 0 (adtp0) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) automatic transmission/reception mode setting <1> set csiae0 and ate0 of serial operating mode specification register 0 (csima0) to 1. <2> set rxea0 and txea0 of csima0 to 1. <3> set a data transfer interval in automatic data transfer interval specification register 0 (adti0). <4> set bit 0 (atsta0) of serial trigger register 0 (csit0) to 1. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data indicated by automatic data transfer address count register 0 (adtc0) is transferred to sioa0, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by adtc0. ? adtc0 is incremented and the next data transmission/reception is carried out. data transmission/reception continues until the adtc0 incremental output matches the set value of automatic data transfer address point specification register 0 (adtp0) (end of automatic transmission/reception). however, if bit 5 (atm0) of csima0 is set to 1 (repeat mode), adtc0 is cleared after a match between adtp0 and adtc0, and then repeated transmission/reception is started. ? when automatic transmission/reception is terminated, tsf0 is cleared to 0. (4) automatic transmission/reception communication operation (a) automatic transmission/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soa0 pin via the sioa0 register in synchronization with the serial clock falling edge by performing (a) and (b) in (3) automatic transmit/receive data setting . the data is then input from the sia0 pin via the sioa0 register in synchronization with the serial clock falling edge and the receive data is stored in the buffer ram in synchronization with the rising edge 1 clock later. data transfer ends if bit 0 (tsf0) of serial status register 0 (csis0) is set to 1 when any of the following conditions is met. ? reset by setting bit 7 (csiae0) of the csima0 register to 0 ? transfer of 1 byte is complete by setting bit 1 (atstp0) of the csit0 register to 1 ? transfer of 1 byte is complete when bit 1 (errf0) of the csis0 register becomes 1 while bit 2 (erre0) = 1 ? transfer of the range specified by the adtp0 register is complete
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 394 at this time, an interrupt request signal (intacsi) is generated except when the csiae0 bit = 0. if a transfer is terminated in the middle, transfer starting from the remaining data is not possible. read automatic data transfer address count register 0 (adtc0) to confirm how much of the data has already been transferred, set the transfer data again, and then re-execute transfer. in addition, when busy control and strobe control are not performed, the busy0/buz/intp7/p141 and stb0/p145 pins can be used as ordinary i/o port pins. figure 17-12 shows the operation timing in automatic transmission/reception mode and figure 17-13 shows the operation flowchart. figure 17-14 shows the operation of internal buffer ram when 6 bytes of data are transmitted/received. figure 17-12. automatic transmission/reception mode operation timings scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer ram after 1- byte transmission/reception, an interval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (6) automatic transmit/receive interval time). 2. when tsf0 is cleared, the soa0 pin becomes low level. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 395 figure 17-13. automatic transmission/reception mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission/reception operation write receive data from sioa0 to internal buffer ram adtp0 = adtc0 no tsf0 = 0 no end yes yes increment pointer value software execution hardware execution software execution adtp0: automatic data transfer address point specification register 0 adti0: automatic data transfer interval specify register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 396 in 6-byte transmission/reception (atm0 = 0, rxea0 = 1, txea0 = 1) in automatic transmission/reception mode, internal buffer ram operates as follows. (i) before transmission/reception (see figure 17-14 (a).) when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when transmission of the first byte is completed, receive data 1 (r1) is transferred from sioa0 to the buffer ram, and automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. (ii) 4th byte transmission/reception point (see figure 17-14 (b).) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to sioa0. when transmission of the fourth byte is completed, the receive data 4 (r4) is transferred from sioa0 to the internal buffer ram, and adtc0 is incremented. (iii) completion of transmission/reception (see figure 17-14 (c).) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sioa0 to the internal buffer ram, and the interrupt request flag (acsiif) is set (intacsi generation). figure 17-14. internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode) (1/2) (a) before transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h receive data 1 (r1) sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 397 figure 17-14. internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode) (2/2) (b) 4th byte transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h receive data 4 (r4) sioa0 0 acsiif 3 adtc0 +1 5 adtp0 (c) completion of transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fa1fh fa05h fa00h sioa0 1 acsiif 5 adtc0 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 398 (b) automatic transmission mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), and bit 3 (txea0) of serial operating mode specification register 0 (csima0) are set to 1. when the final byte has been transmitted, an interrupt request flag (acsiif) is set. however, judge the termination of automatic transmission and reception, not by acsiif but by bit 0 (tsf0) of serial status register 0 (csis0). if a receive operation, busy control and strobe control are not executed, the busy0/buz/intp7/p141 and stb0/p145 pins can be used as normal i/o port pins. figure 17-15 shows the automatic transmission mode operation timing, and figure 17-16 shows the operation flowchart. figure 17-17 shows the operation of the internal buffer ram when 6 bytes of data are transmitted or received. figure 17-15. automatic transmission mode operation timing scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 interval cautions 1. because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer ram after 1-byte transmission, an interval is inserted until the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (6) automatic transmit/receive interval time). 2. when tsf0 is cleared, the soa0 pin becomes low level. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 399 figure 17-16. automatic transmission mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no tsf0 = 0 no end yes yes increment pointer value software execution hardware execution software execution adtp0: automatic data transfer address point specification register 0 adti0: automatic data transfer interval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 400 in 6-byte transmission (atm0 = 0, rxea0 = 0, txea0 = 1, ate0 = 1) in automatic transmission mode, internal buffer ram operates as follows. (i) before transmission (see figure 17-17 (a).) when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when transmission of the first byte is completed, automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. (ii) 4th byte transmission point (see figure 17-17 (b).) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to sioa0. when transmission of the fourth byte is completed, adtc0 is incremented. (iii) completion of transmission (see figure 17-17 (c).) when transmission of the sixth byte is completed, the interrupt request flag (acsiif) is set (intacsi generation). figure 17-17. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (1/2) (a) before transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 401 figure 17-17. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (2/2) (b) 4th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 3 adtc0 +1 5 adtp0 (c) completion of transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 1 acsiif 5 adtc0 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 402 (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial transfer is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), bit 5 (atm0), and bit 3 (txea0) of serial operating mode specification register 0 (csima0) are set to 1. unlike the basic transmission mode, after the final byte (data in address fa1fh) has been transmitted, the interrupt request flag (acsiif) is not set, the automatic data transfer address count register 0 (adtc0) is reset to 0, and the internal buffer ram contents are transmitted again. when a reception operation, busy control and strobe control are not performed, the busy0/buz/intp7/p141 and stb0/p145 pins can be used as ordinary i/o port pins. the repeat transmission mode operation timing is shown in figure 17-18, and the operation flowchart in figure 17-19. figure 17-20 shows the operation of the internal buffer ram when 6 bytes of data are transmitted in the repeat transmission mode. figure 17-18. repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 scka0 soa0 caution because, in the repeat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon automatic data transfer interval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (6) automatic transmit/receive interval time).
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 403 figure 17-19. repeat transmission mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no yes increment pointer value software execution hardware execution reset adtc0 to 0 adtp0: automatic data transfer address point specification register 0 adti0: automatic data transfer interval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 404 in 6-byte transmission (atm0 = 1, rxea0 = 0, txea0 = 1, ate0 = 1) in repeat transmission mode, internal buffer ram operates as follows. (i) before transmission (see figure 17-20 (a).) when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when transmission of the first byte is completed, automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. (ii) upon completion of transmission of 6 bytes (see figure 17-20 (b).) when transmission of the sixth byte is completed, the interrupt request flag (acsiif) is not set. adtc0 is reset to 0. (iii) 7th byte transmission point (see figure 17-20 (c).) transmit data 1 (t1) is transferred from the internal buffer ram to sioa0 again. when transmission of the first byte is completed, adtc0 is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. figure 17-20. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (1/2) (a) before transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 405 figure 17-20. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 5 adtc0 5 adtp0 (c) 7th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 406 (d) data format in the data format, data is changed in synchronization with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-21. format of csia0 transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 407 (e) automatic transmission/reception suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1. during 8-bit data transfer, the transmission/reception is not suspended. it is suspended upon completion of 8-bit data transfer. when suspended, bit 0 (tsf0) of serial status register 0 (csis0) is set to 0 after transfer of the 8th bit, and all the port pins that function alternately as (p141/buz/busy0/intp7, p142/scka0, p143/sia0, p144/soa0, and p145/stb0) are set to the port mode. to restart automatic transmission/reception, set bit 0 (atsta0) of csit0 to 1. the remaining data can be transmitted in this way. cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set if during 8-bit data transfer. when the halt mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. when suspending automatic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while tsf0 = 1. figure 17-22. automatic transmission/reception suspension and restart scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command atsta0 = 1 suspend atstp0 = 1 (suspend command) atstp0: bit 1 of serial trigger register 0 (csit0) atsta0: bit 0 of csit0
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 408 (5) synchronization control busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. by using these functions, a shift in bits being transmitted or received can be detected. (a) busy control option busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. when using this busy control option, the following conditions must be satisfied. ? bit 6 (ate0) of serial operating mode specification register 0 (csima0) is set to 1. ? bit 4 (busye0) of serial status register 0 (csis0) is set to 1. figure 17-23 shows the system configuration of the master device and slave device when the busy control option is used. figure 17-23. system configuration when busy control option is used scka0 soa0 sia0 scka0 sia0 soa0 busy0 master device (78k0/kf1 series) slave device the master device inputs the busy signal output by the slave device to the busy0/buz/intp7/p141 pin. the master device samples the input busy signal in synchronization with the falling of the serial clock. even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. if the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. after that, the master transmission/reception is kept waiting while the busy signal is active. the active level of the busy signal is set by bit 3 (busylv0) of csis0. busylv0 = 1: active-high busylv0 = 0: active-low when using the busy control option, select the internal clock as the serial clock. control with the busy signal cannot be implemented with the external clock. figure 17-24 shows the operation timing when the busy control option is used. caution busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (adti0). if used, busy control is invalid.
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 409 figure 17-24. operation timing when busy control option is used (when busylv0 = 1) scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 tsf0 clears busy input busy input is valid wait caution if the tsf0 is cleared, the soa0 pin goes low. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) when the busy signal becomes inactive, waiting is released. if the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. it takes 0.5 clock until data transfer is started after the busy signal was sampled. to accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clock. figure 17-25 shows the timing of the busy signal and releasing the waiting. this figure shows an example in which the busy signal is active as soon as transmission/reception has been started. figure 17-25. busy signal and wait release (when busylv0 = 1) scka0 d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 (active-high) 1.5 clocks (min.) busy input released busy input valid wait if made inactive immediately after sampled
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 410 (b) busy & strobe control option strobe control is a function used to synchronize data transmission/reception between the master and slave devices. the master device outputs the strobe signal from the stb0/p145 pin when 8-bit transmission/reception has been completed. by this signal, the slave device can determine the timing of the end of data transmission. therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. to use the strobe control option, the following conditions must be satisfied: ? bit 6 (ate0) of the serial operating mode specification register 0 (csima0) is set to 1. ? bit 5 (stbe0) of serial status register 0 (csis0) is set to 1. usually, the busy control and strobe control options are simultaneously used as handshake signals. in this case, the strobe signal is output from the stb0/p145 pin, the busy0/buz/intp7/p141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. a high level lasting for one transfer clock is output from the stb0/p145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. the busy signal is detected at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. when the strobe control option is not used, the p145/stb0 pin can be used as a normal i/o port pin. figure 17-26 shows the operation timing when the busy & strobe control options are used. when the strobe control option is used, the interrupt request flag (acsiif) that is set on completion of transmission/reception is set after the strobe signal is output. figure 17-26. operation timing when busy & strobe control options are used (when busylv0 = 1) stb0 scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 tsf0 busy input released busy input valid caution when tsf0 is cleared, the soa0 pin goes low. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 411 (c) bit shift detection by busy signal during automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. in this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. a bit shift is detected by using the busy signal as follows: the slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). the master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (erre0) of serial status register 0 (csis0) is set to 1. if a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. if the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (errf0) of serial status register 0 (csis0) to 1, and transfer is suspended and an interrupt request signal (intacsi) is output). although transfer is suspended after completion of 1-byte data transfer, slave signal output, wait due to the busy signal, and wait due to the interval time specified by adti0 are not executed. if erre0 = 0, errf0 cannot become 1 even if a bit shift occurs. figure 17-27 shows the operation timing of the bit shift detection function by the busy signal. remark the bit error function is valid both in the master mode and slave mode. the setting of erre0 is valid even when busye0 = 0. figure 17-27. operation timing of bit shift detection function by busy signal (when busylv0 = 0) scka0 (slave) d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 acsiif csiae0 errf0 d7 d7 busy not detected error interrupt request generated error detected bit shift due to noise scka0 (master) acsiif: interrupt request flag csiae0: bit 7 of serial operating mode specification register 0 (csima0) errf0: bit 1 of serial status register 0 (csis0)
chapter 17 serial interface csia0 preliminary user ? s manual u15947ej1v1ud 412 (6) automatic transmit/receive interval time when using the automatic transmit/receive function, the read/write operations from/to the internal buffer ram are performed after transmitting/receiving one byte. therefore, an interval is inserted before the next transmit/receive operation. since the read/write operations from/to the buffer ram are performed in parallel with the cpu processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic data transfer interval specification register 0 (adti0) and bits 5 and 4 (stbe0, busye0) of the serial status register 0 (csis0). when adti0 is set to 00h, an interval time based on the to stbe0 and busye0 settings is generated. for example, when adti0 = 00h and stbe0 = busye0 = 1, an interval time of two clocks is generated. if an interval time of two clocks or more is set by adti0, the interval time set by adti0 is generated regardless of the stbe0 and busye0 settings. example <1> when stbe0 = 1, busye0 = 0: interval time of two transfer clocks is generated <2> when stbe0 = 0, busye0 = 1: interval time of one transfer clock is generated <3> when stbe0 = 1, busye0 = 1: interval time of two transfer clocks is generated figure 17-28. automatic data transmit/receive interval time scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval acsiif: interrupt request flag
preliminary user?s manual u15947ej1v1ud 413 chapter 18 multiplier/divider 18.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 16 bits = 32 bits, 16-bit remainder (division) 18.2 configuration of multiplier/divider the multiplier/divider consists of the following hardware. table 18-1. configuration of multiplier/divider item configuration registers remainder data register 0 (sdr0) multiplication/division data registers a0 (mda0h, mda0l) multiplication/division data registers b0 (mdb0) control register multiplier/divider control register 0 (dmuc0) figure 18-1 shows the block diagram of the multiplier/divider.
chapter 18 multiplier/divider preliminary user?s manual u15947ej1v1ud 414 figure 18-1. block diagram of multiplier/divider internal bus cpu clock start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h+mdb0l) remainder data register 0 (sdr0 (sdr0h+sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 ( mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll) ) controller dmue mda000 intdmu
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 415 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. this register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. this register can be read by an 8-bit or 16-bit memory manipulation instruction. reset input sets this register to 0000h. figure 18-2. format of remainder data register 0 (sdr0) address: ff60h, ff61h after reset: 0000h r symbol ff61h ff60h sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 during operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1). (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a register that stores 16-bit multiplier a in the multiplication mode, and a 32-bit dividend in the division mode (higher 16 bits: mda0h, lower 16 bits: mda0l, mda0h+mda0l: mda0). the functions of mda0 when an operation is executed are shown in the table below. table 18-2. functions of mda0 during operation execution dmusel0 note operation mode setting operation result 0 division mode dividend division result (quotient) 1 multiplication mode higher 10 bits: 0, lower 16 bits: multiplier a multiplication result (product) the register configuration differs between when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication mda0 (bits 15 to 0) mdb0 (bits 15 to 0) = mda0 (bits 31 to 0) ? register configuration during division mda0 (bits 31 to 0) mdb0 (bits 15 to 0) = mda0 (bits 31 to 0) ? sdr0 (bits 15 to 0) mda0 fetches the calculation result as soon as the clock is input, when bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is set to 1. mda0h and mda0l can be set by an 8-bit or 16-bit memory instruction. reset input sets this register to 0000h.
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 416 figure 18-3. format of multiplication/division data register a0 (mda0h, mda0l) address: ff62h, ff63h, ff64h, ff65h after reset: 0000h, 0000h r/w symbol ff65h (mda0hh) ff64h (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff63h (mda0lh) ff62h (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is reset to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 during operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 3. the value read from mda0 during operation processing (while dmue is 1) is not guaranteed. (3) multiplication/division data register b0 (mdb0) mdb0 is a register that stores a 16-bit multiplier b in the multiplication mode and a 16-bit divisor in the division mode. this register can be set by an 8-bit or 16-bit memory manipulation instruction. reset input sets this register to 0000h. figure 18-4. format of multiplication/division data register b0 (mdb0) address: ff66h, ff67h after reset: 0000h r/w symbol ff67h ff66h mdb0 mdb 015 mdb 014 mdb 013 mdb 012 mdb 011 mdb 010 mdb 009 mdb 008 mdb 007 mdb 006 mdb 005 mdb 004 mdb 003 mdb 002 mdb 001 mdb 000 cautions 1. do not change the value of mdb0 during operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 2. do not set mdb0 to 0000h in the division mode. if set, undefined operation results are stored in mda0 and sdr0.
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 417 18.3 register controlling multiplier/divider the multiplier/divider is controlled by multiplier/divider control register 0 (dmuc0). (1) multiplier/divider control register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 18-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff68h after reset: 00h r/w symbol 4 3 2 1 0 6 75 note when dmue is set to 1, the operation is started. dmue is automatically cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during operation processing (when dmue is 1), the operation result is not guaranteed. if the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (while dmue is 1). if it is changed, undefined operation results are stored in multiplication/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during operation processing (while dmue is 1), the operation processing is stopped. to execute the operation again, set multiplication/division data register a0 (mda0), multiplication/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and start the operation (by clearing dmue to 0).
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 418 18.4 operations of multiplier/divider 18.4.1 multiplication operation (1) multiplication operation ? initial setting 1. set operation data to multiplication/division data register a0l (mda0l) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 1. the internal clock will start (operation will start). ? during operation 3. the operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0h registers during operation, and therefore the read values of these registers are not guaranteed). ? end of operation 4. after the operation, an interrupt request signal (intdmu) is generated. 5. the operation result data is stored in the mda0l and mda0h registers. 6. dmue is cleared to 0 (end of operation). ? next operation 7. to execute multiplication next, start from the initial setting in 18.4.1 multiplication operation (1) . 8. to execute division next, start from the initial setting in 18.4.2 division operation (1) .
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 419 figure 18-6. timing chart of multiplication operation (00dah 0093h) cpu clock mda0 sdr0 mdb0 1 2 345 6 78 9a b cd e f 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006d 0000 00da xxxx 00da xxxx xxxx xxxx 0049 8036 0024 c01b 005b e00d 0077 7006 003b b803 0067 5c01 007d 2e00 003e 9700 001f 4b80 000f a5c0 0007 d2e0 0003 e970 0001 f4b8 0000 fa5c 0000 7d2e 0093 xxxx internal clock dmue dmusel0 counter intdmu
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 420 (2) multiplication operation ? ? ? ? multiplication operation 1. after the operation, an interrupt request signal (intdmu) is generated. 2. the operation result data is stored in multiplication/division data register a0 (mda0l and mda0h). 3. bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is cleared to 0 (end of operation). ? initial setting 4. set operation data to multiplication/division data register a0l (mda0l) and multiplication/division data register b0 (mdb0). 5. set bits 0 (dmusel0) and 7 (dmue) of dmuc0 to 1. the internal clock will start (operation will start). ? during operation 6. the operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0h registers during operation, and therefore the read values of these registers are not guaranteed).
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 421 cpu clock mda0 sdr0 mdb0 12 e f 10 0 0 0000 0000 0000 0000 0000 0000 0000 006d 0000 00da xxxx 00da xxxx xxxx xxxx 0049 8036 0001 f4b8 0000 fa5c 0000 7d2e 0093 xxxx internal clock dmue dmusel0 counter intdmu 0000 ffff ffff ffff 7fff ffff bfff 7fff 0000 0000 0000 12 ffff figure 18-7. timing chart when multiplication is executed successively (00dah 0093h ffffh ffffh)
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 422 as an example, the calculation of ? 4 bits 4 bits (0111b 0101b) ? is shown below. figure 18-8. example of multiplication operation by multiplier/divider (4 bits 4 bits (0111b 0101b)) 1. if the least significant bit of the multiplicand register whose most significant bit is zero-extended is 1, the multiplier with the most significant bit zero-extended is added to the higher 5 bits of the multiplicand register. 2. if the least significant bit of the multiplicand register whose most significant bit is zero-extended is 0, zero is added to the higher 5 bits of the multiplicand register. 3. after addition, the lower 4 bits of the multiplicand register are shifted 1 bit to the right, and the product with the most significant bit of the addition result zero-extended is stored in the higher 5 bits. 0 0000 0 0101 0 0101 + 0 0010 0 0101 0 0111 + 0 0000 011 1 0 00101 011 0 0010 101 1 0 00111 101 0 0011 110 1 0 0011 0 0101 0 1000 + 0 01000 110 0 0100 011 0 0 0100 0 0000 0 0100 + 0 00100 011 product multiplicand zero-extended
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 423 18.4.2 division operation (1) division operation ? initial setting 1. set operation data to multiplication/division data register a0 (mda0l and mda0h) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. the internal clock will start (operation will start). ? during operation 3. the operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0h registers and remainder data register 0 (sdr0) during operation, and therefore the read values of these registers are not guaranteed). ? end of operation 4. after the operation, an interrupt request signal (intdmu) is generated. 5. the result data is stored in the mda0l, mda0h, and sdr0 registers. 6. dmue is cleared to 0 (end of operation). ? next operation 7. to execute multiplication next, start from the initial setting in 18.4.1 multiplication operation (1) . 8. to execute division next, start from the initial setting in 18.4.2 division operation (1) .
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 424 figure 18-9. timing chart of division operation (dcba2586h 0018h) cpu clock mda0 sdr0 mdb0 12345678 19 1a 1b 1c 1d 1e 1f 20 0 0 0000 0001 0003 0006 000d 0003 0007 000e 0004 000b 0016 0014 0010 0008 0011 000b 0016 b974 4b0c dcba 2586 xxxx xxxx xxxx 72e8 a618 e5d1 2c30 cba2 6860 a744 bac1 2e89 6182 6d12 c304 ba25 8609 0c12 64d8 1824 c9b0 3049 9361 6093 26c3 c126 4d87 824c 9b0e 0499 361d 0932 6c3a 0018 xxxx internal clock dmue dmusel0 counter intdmu "0"
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 425 (2) division operation ? ? ? ? division operation 1. after the operation, an interrupt request signal (intdmu) is generated. 2. the result data is stored in multiplication/division data register a0 (mda0l and mda0h) and remainder data register 0 (sdr0). 3. bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is cleared to 0 (end of operation). ? initial setting 4. set operation data to the mda0l, mda0h, and mdb0 registers. 5. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. the internal clock will start (operation will start). ? during operation 6. the operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l, mda0h, and sdr0 registers during operation, and therefore the read values of these registers are not guaranteed).
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 426 figure 18-10. timing chart when division is executed successively (dcba2586 0018h ffffffffh ffffh) cpu clock mda0 sdr0 mdb0 12 1e 1f 20 0 0 0000 0001 0003 0011 000b 0016 b974 4b0c dcba 2586 xxxx xxxx xxxx 72e8 a618 824c 9b0e 0499 361d 0932 6c3a 0093 xxxx internal clock dmue dmusel0 counter intdmu ffff ffff ffff fffe ffff fffc 0000 0001 0003 12 ffff "0"
chapter 18 multiplier/divider preliminary user ? s manual u15947ej1v1ud 427 as an example, the calculation of ? 4 bits 2 bits (1001b 10b) ? is shown below. figure 18-11. example of division operation by multiplier/divider (4 bits 2 bits (1001b 10b)) 1. the inverted value of the higher 3 bits of the dividend register whose most significant bit is extended by ? 00 ? is added to the divisor whose most significant bit is zero-extended. 2. after addition, the dividend register is shifted 1 bit to the left and ? 0 ? is stored in the least significant bit if the most significant bit is 0. 3. if the most significant bit is 1 after addition, the dividend register is shifted 1 bit to the left, and the inverted addition result, except the most significant bit, is stored in the higher 2 bits of the dividend register. 1 is stored in the least significant bit. 4. the higher 2 bits of the dividend register indicate the remainder, while the lower 4 bits indicate the quotient. 5. after addition, the lower 4 bits of the dividend register are shifted 1 bit to the right, and the addition result whose most significant bit is zero-extended is stored in the higher 5 bits. 110 010 0 00 + 001 001 010 01 0 dividend zero-extended inverted left shift 101 010 1 11 + inverted 000 10 1 inverted and stored left shift 111 010 0 01 + inverted 001 01 0 left shift inverted 110 010 0 00 + 01010 0 left shift quotient = 0100b remainder = 01b
preliminary user?s manual u15947ej1v1ud 428 chapter 19 interrupt functions 19.1 interrupt function types the following two types of interrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see table 19-1 ). a standby release signal is generated. nine external interrupt requests and 20 (17 in the pd780143 and 780144) internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration a total of 30 (27 in the pd780143 and 780144) interrupt sources exist for maskable and software interrupts (see table 19-1 ).
chapter 19 interrupt functions preliminary user?s manual u15947ej1v1ud 429 table 19-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 transfer/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and crh1 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and crh0 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad end of a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intwti watch timer reference time interval signal 0028h maskable 19 inttm51 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 19-1.
chapter 19 interrupt functions preliminary user?s manual u15947ej1v1ud 430 table 19-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 20 intkr key interrupt detection external 002ch (c) 21 intwt watch timer overflow internal 002eh (a) 22 intp6 0030h 23 intp7 pin input edge detection external 0032h (b) 24 intdmu end of multiply/divide operation 0034h 25 intcsi11 note 3 end of csi11 transfer 0036h 26 inttm001 note 3 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 0038h 27 inttm011 note 3 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) 003ah maskable 28 intacsi end of csia0 transfer internal 003ch (a) software ? brk brk instruction execution ? 003eh (d) reset reset input poc power-on reset lvi low-voltage detection clock monitor x1 oscillation stop detection reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 19-1. 3. the interrupt sources intcsi11, inttm001, and inttm011 are available only in the pd780146, 780148, and 78f0148.
chapter 19 interrupt functions preliminary user?s manual u15947ej1v1ud 431 figure 19-1. basic configuration of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable interrupt (intp0 to intp7) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 432 figure 19-1. basic configuration of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 7) (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register 19.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 433 table 19-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt request register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 dualif0 note 1 dualmk0 note 1 dualpr0 note 1 intst0 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif if1l admk mk1l adpr pr1l intsr0 srif0 srmk0 srpr0 intwti wtiif wtimk wtipr inttm51 tmif51 tmmk51 tmpr51 intkr krif krmk krpr intwr wtif wtmk wtpr intp6 pif6 pmk6 ppr6 intp7 pif7 pmk7 ppr7 intsr0 srif0 srmk0 srpr0 intdmu dmuif if1h dmumk mk1h dmupr pr1h intcsi11 note 2 csiif11 note 2 csimk11 note 2 csipr11 note 2 inttm001 note 2 tmif001 note 2 tmmk001 note 2 tmpr001 note 2 inttm011 note 2 tmif011 note 2 tmmk011 note 2 tmpr011 note 2 intacsi acsiif acsimk acsipr notes 1. if either of the two types of interrupt sources is generated, these flags are set (1). 2. pd780146, 780148, and 78f0148 only.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 434 (1) interrupt request flag registers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are set by a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol76543210 if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol76543210 if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol76543210 if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol76543210 if1h 0 note 1 0 note 1 0 note 1 acsiif tmif011 note 2 tmif001 note 2 csiif11 note 2 dmuif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. be sure to set bits 5 to 7 of if1h to 0. 2. pd780146, 780148, and 78f0148 only. be sure to set these bits to 0 in the pd780143 and 780144. cautions 1. when operating a timer, serial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 2. when an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 435 (2) interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set by a 16-bit memory manipulation instruction. reset input sets mk0l, mk0h, and mk1l to ffh and mk1h to dfh. figure 19-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol76543210 mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol76543210 mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol76543210 mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: dfh r/w symbol76543210 mk1h 1 note 1 1 note 1 0 note 1 acsimk tmmk011 note 2 tmmk001 note 2 csimk11 note 2 dmumk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. be sure to set bits 6 and 7 of mk1h to 1 and bit 5 to 0. 2. pd780146, 780148, and 78f0148 only. be sure to set these bits to 1 in the pd780143 and 780144.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 436 (3) priority specification flag registers (pr0l, pr0h, pr1l, pr1h) the priority specification flag registers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol76543210 pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol76543210 pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpro stpr6 srpr6 address: ffeah after reset: ffh r/w symbol76543210 pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol76543210 pr1h 1 note 1 1 note 1 1 note 1 acsipr tmpr011 note 2 tmpr001 note 2 csipr11 note 2 dmupr xxprx priority level selection 0 high priority level 1 low priority level notes 1. be sure to set bits 5 to 7 of pr1h to 1. 2. pd780146, 780148, and 78f0148 only. be sure to set these bits to 1 in the pd780143 and 780144.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 437 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol76543210 egp egp7 epg6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol76543210 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 interrupt disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 19-3 shows the ports corresponding to egpn and egnn. table 19-3. ports corresponding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 438 (5) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status for an interrupt request. the ie flag that sets maskable interrupt enable/disable and the isp flag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-6. format of program status word 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgement enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 439 19.4 interrupt servicing operations 19.4.1 maskable interrupt request acknowledgement a maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-4 below. for the interrupt request acknowledgement timing, see figures 19-8 and 19-9 . table 19-4. time from generation of maskable interrupt request until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. if two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 19-7 shows the interrupt request acknowledgement algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data determined for each interrupt request is loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 440 figure 19-7. interrupt request acknowledgement processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of maskable interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 441 figure 19-8. interrupt request acknowledgement timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-9. interrupt request acknowledgement timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.2 software interrupt request acknowledgement a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possible by using the retb instruction. caution do not use the reti instruction for restoring from the software interrupt.
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 442 19.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (ie = 1). also, when an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgement. moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of one main processing instruction execution. table 19-5 shows interrupt requests enabled for multiple interrupt servicing and figure 19-10 shows multiple interrupt servicing examples. table 19-5. interrupt request enabled for multiple interrupt servicing during interrupt servicing multiple interrupt request maskable interrupt request pr = 0 pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 isp = 0 maskable interrupt isp = 1 software interrupt remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgement is disabled. ie = 1: interrupt request acknowledgement is enabled. 4. pr is a flag contained in pr0l, pr0h, pr1l, and pr1h. pr = 0: higher priority level pr = 1: lower priority level
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 443 figure 19-10. examples of multiple interrupt servicing (1/2) example 1. multiple interrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgement. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgement disabled
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 444 figure 19-10. examples of multiple interrupt servicing (2/2) example 3. multiple interrupt servicing does not occur because interrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgement disabled
chapter 19 interrupt functions preliminary user ? s manual u15947ej1v1ud 445 19.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. figure 19-11 shows the timing at which interrupt requests are held pending. figure 19-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request).
preliminary user?s manual u15947ej1v1ud 446 chapter 20 key interrupt function 20.1 functions of key interrupt a key interrupt (intkr) can be generated by setting the key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 20-1. assignment of key interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 20.2 configuration of key interrupt the key interrupt consists of the following hardware. table 20-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 20-1. block diagram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
chapter 20 key interrupt function preliminary user ? s manual u15947ej1v1ud 447 20.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. this register is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 20-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the interrupt request flag and enable interrupts. 3. the bits not used in the key interrupt mode can be used as normal ports.
preliminary user?s manual u15947ej1v1ud 448 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function table 21-1. relationship between halt mode, stop mode, and clock x1 input clock ring-osc clock subsystem clock cpu clock halt mode oscillation continues oscillation continues oscillation continues operation stopped stop mode oscillation stopped oscillation continues oscillation continues operation stopped the standby function is designed to reduce the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. in the halt mode, the cpu operation clock is stopped, but the system clock oscillator continues oscillating. in this mode, current consumption is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the x1 input clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to secure the oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. stop mode can be used only when operating on the x1 input clock or ring-osc clock. halt mode can be used when operating on the x1 input clock, ring-osc clock, or subsystem clock. however, when the stop instruction is executed during ring-osc clock operation, the x1 oscillator stops, but ring-osc oscillator does not stop. 2. when shifting to the stop mode, be sure to stop the peripheral hardware operation before executing stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 4. ring-osc clock oscillation cannot be stopped in the stop mode. however, when the ring- osc clock is used as the cpu clock, the cpu operation is stopped for 17/f r (s) after stop mode is released.
chapter 21 standby function preliminary user?s manual u15947ej1v1ud 449 figure 21-1. operation timing when stop mode is released ring-osc clock is selected as cpu clock when stop instruction is executed ring-osc clock x1 input clock x1 input clock is selected as cpu clock when stop instruction is executed stop mode release stop mode operation stopped (17/f r ) clock switched by software ring-osc clock x1 input clock halt status (oscillation stabilization time set by osts) x1 input clock
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 450 21.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time counter status register (ostc) ? oscillation stabilization time select register (osts) (1) oscillation stabilization time counter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. reset input, stop instruction, mstop = 1, and mcc = 1 clear ostc to 00h. figure 21-2. format of oscillation stabilization time counter status register (ostc) address: ffa3h after reset: 00h r symbol76543210 ostc 0 0 0 most11 most13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 10000 2 11 /f x min. (204.8 s min.) 11000 2 13 /f x min. (819.2 s min.) 111002 14 /f x min. (1.64 ms min.) 111102 15 /f x min. (3.27 ms min.) 111112 16 /f x min. (6.55 ms min.) caution after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. remarks 1. values in parentheses are for operation with f x = 10 mhz. 2. f x : x1 input clock oscillation frequency
chapter 21 standby function preliminary user?s manual u15947ej1v1ud 451 (2) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabilization wait time when stop mode is released. the wait time set by osts is valid only after stop mode is released when the x1 input clock is selected as the cpu clock. after stop mode is released when the ring-osc clock is selected, check the oscillation stabilization time using ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 21-3. format of oscillation stabilization time select register (osts) address: ffa4h after reset: 05h r/w symbol76543210 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 001 2 11 /f x (204.8 s) 010 2 13 /f x (819.2 s) 0112 14 /f x (1.64 ms) 1002 15 /f x (3.27 ms) 1012 16 /f x (6.55 ms) other than above setting prohibited cautions 1. if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? ? ? ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only during the oscillation stabilization time set by osts. therefore, note that only the statuses during the oscillation stabilization time set by osts are set to ostc after stop mode has been released. 2. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. stop mode release x1 pin voltage waveform v ss a remarks 1. values in parentheses are for operation with f x = 10 mhz. 2. f x : x1 input clock oscillation frequency
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 452 21.2 standby function operation 21.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the x1 input clock, ring-osc clock, or subsystem clock. the operating statuses in the halt mode are shown below. table 21-2. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on x1 input clock when halt instruction is executed while cpu is operating on ring-osc clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock the x1 oscillator, ring-osc oscillator, and subsystem clock oscillator are able to oscillate. clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation stopped 16-bit timer/event counter 01 note 2 operable operation stopped 8-bit timer/event counter 50 operable operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable operable only when ti51 is selected as the count clock 8-bit timer h0 operable operable only when to50 is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operable only when f r /2 7 is selected as the count clock watch timer operable operable note 3 operable operable note 3 operable note 4 not operable operable note 4 not operable ring-osc cannot be stopped note 5 operable ? operable watchdog timer ring-osc can be stopped note 5 operation stopped a/d converter operable not operable uart0 operable uart6 operable operable only when to50 is selected as the serial clock during tm50 operation csi10 operable operable only when external sck10 is selected as the serial clock csi11 note 2 operable operable only when external sck11 is selected as the serial clock serial interface csia0 operable operation stopped clock monitor operable operation stopped operable operation stopped multiplier/divider operable operation stopped power-on-clear function note 6 operable low-voltage detection function operable external interrupt operable notes 1. when ? stopped by software ? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 27 mask options ). 2. pd780146, 780148, and 78f0148 only. 3. operable when the x1 input clock is selected. 4. operable when the subsystem clock is selected. 5. ? ring-osc cannot be stopped ? or ? ring-osc can be stopped by software ? can be selected by a mask option. 6. when ? poc used ? is selected by a mask option.
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 453 table 21-2. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when ring-osc oscillation continues when ring-osc oscillation stopped note 1 system clock the x1 oscillator, ring-osc oscillator, and subsystem clock oscillator are able to oscillate. clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation stopped 16-bit timer/event counter 01 note 2 operable operation stopped 8-bit timer/event counter 50 operable operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable operable only when ti51 is selected as the count clock 8-bit timer h0 operable operable only when to50 is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operable only when the x1 input clock is selected as the count clock operable only when f r /2 7 is selected as the count clock operation stopped watch timer operable operable only when subsystem clock is selected ring-osc cannot be stopped note 3 operable ? operable ? watchdog timer ring-osc can be stopped note 3 operation stopped a/d converter operable not operable uart0 operable uart6 operable operable only when to50 is selected as the serial clock during tm50 operation csi10 operable operable only when external clock is selected as the serial clock csi11 note 2 operable operable only when external clock is selected as the serial clock serial interface csia0 operable operation stopped clock monitor operable operation stopped multiplier/divider operable operation stopped power-on-clear function note 4 operable low-voltage detection function operable external interrupt operable notes 1. when ? stopped by software ? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 27 mask options ). 2. pd780146, 780148, and 78f0148 only. 3. ? ring-osc cannot be stopped ? or ? ring-osc can be stopped by software ? can be selected by a mask option. 4. when ? poc used ? is selected by a mask option.
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 454 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 21-4. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation x1 input clock, ring-osc clock, or subsystem clock cpu clock standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 455 (b) release by reset input when the reset signal is input, halt mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. figure 21-5. halt mode release by reset input (1) when x1 input clock is used as cpu clock halt instruction reset signal x1 input clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates cpu clock (x1 input clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) (ring-osc clock) (17/f r ) (2) when ring-osc clock or subsystem clock is used as cpu clock halt instruction reset signal ring-osc clock or subsystem clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates cpu clock (ring-osc clock) (17/f r ) ring-osc clock or subsystem clock remarks 1. f x : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 21-3. operation after halt mode release release source mk pr ie isp operation 000 next address instruction execution 001 interrupt servicing execution 0101 01 0 next address instruction execution 0111interrupt servicing execution maskable interrupt request 1 halt mode held reset input ?? reset processing : don't care
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 456 21.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing the stop instruction, and it can be set only when the cpu clock before the setting was the x1 input clock or ring-osc clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (osts) has elapsed. the operating statuses in the stop mode are shown below. table 21-4. operating statuses in stop mode when stop instruction is executed while cpu is operating on x1 input clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when stop instruction is executed while cpu is operating on ring- osc clock stop mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock only x1 oscillator oscillation is stopped. clock supply to the cpu is stopped. cpu operation stopped port (latch) status before stop mode was set is retained 16-bit timer/event counter 00 operation stopped 16-bit timer/event counter 01 note 2 operation stopped 8-bit timer/event counter 50 operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable only when ti51 is selected as the count clock 8-bit timer h0 operable only when to50 is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable note 3 operation stopped operable note 3 watch timer operable note 4 operation stopped operable note 4 operation stopped operable note 4 operation stopped ring-osc cannot be stopped note 5 operable ? operable watchdog timer ring-osc can be stopped note 5 operation stopped a/d converter operation stopped uart0 uart6 operable only when to50 is selected as the serial clock during tm50 operation csi10 operable only when external sck10 is selected as the serial clock csi11 note 2 operable only when external sck11 is selected as the serial clock serial interface csia0 operation stopped clock monitor operation stopped multiplier/divider operation stopped power-on-clear function note 6 operable low-voltage detection function operable external interrupt operable notes 1. when ? stopped by software ? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 27 mask options ). 2. pd780146, 780148, and 78f0148 only. 3. operation continues only when f r /2 7 is selected as the count clock. 4. operable when the subsystem clock is selected. 5. ? ring-osc cannot be stopped ? or ? ring-osc can be stopped by software ? can be selected by a mask option. 6. when ? poc used ? is selected by a mask option.
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 457 (2) stop mode release the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 21-6. stop mode release by interrupt request generation (1) when x1 input clock is used as cpu clock operating mode operating mode oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait status oscillation stopped x1 input clock cpu clock oscillation stabilization time (set by osts) (x1 input clock) (x1 input clock) (2) when ring-osc clock is used as cpu clock operating mode operating mode oscillates stop instruction stop mode standby release signal ring-osc clock cpu clock (ring-osc clock) operation stopped (17/ f r ) (ring-osc clock) remark the broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
chapter 21 standby function preliminary user ? s manual u15947ej1v1ud 458 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 21-7. stop mode release by reset input (1) when x1 input clock is used as cpu clock stop instruction reset signal x1 input clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates cpu clock (x1 input clock) oscillation stabilization time (2 11/ f x to 2 16 /f x ) (ring-osc clock) (17/f r ) oscillation stopped (2) when ring-osc clock is used as cpu clock stop instruction reset signal ring-osc clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates cpu clock (ring-osc clock) (17/f r ) (ring-osc clock) table 21-5. operation after stop mode release release source mk pr ie isp operation 000 next address instruction execution 001 interrupt servicing execution 0101 01 0 next address instruction execution 0111interrupt servicing execution maskable interrupt request 1 stop mode held reset input ?? reset processing : don't care
preliminary user?s manual u15947ej1v1ud 459 chapter 22 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by clock monitor x1 clock oscillation stop detection (4) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (5) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, x1 clock oscillation stop is detected by the clock monitor, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in table 22-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and program execution starts using the ring- osc clock after the cpu clock operation has stopped for 17/f r (s). a reset generated by the watchdog timer and clock monitor sources is automatically released after the reset, and program execution starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see figures 22-2 to 22-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and program execution starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see chapter 24 power-on-clear circuit and chapter 25 low-voltage detector ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 input clock and ring-osc clock stop oscillating. 3. when the stop mode is released by a reset, the stop mode contents are held during reset input. however, the port pins become high-impedance, except for p130, which is set to low- level output.
chapter 22 reset function preliminary user?s manual u15947ej1v1ud 460 figure 22-1. block diagram of reset function clmrf lvirf wdtrf reset control flag register (resf) internal bus wdtres (watchdog timer reset signal) clmresb (clock monitor reset signal) reset pocresb (power-on-clear circuit reset signal) lviresb (low-voltage detector reset signal) reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal reset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register
chapter 22 reset function preliminary user ? s manual u15947ej1v1ud 461 figure 22-2. timing of reset by reset input delay delay hi-z note normal operation reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 reset internal reset signal port pin cpu clock figure 22-3. timing of reset due to watchdog timer overflow hi-z note normal operation reset period (oscillation stop) x1 watchdog timer overflow internal reset signal port pin operation stop (17/f r ) normal operation (reset processing, ring-osc clock) cpu clock caution a watchdog timer internal reset resets the watchdog timer. figure 22-4. timing of reset in stop mode by reset input delay delay hi-z note normal operation x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) cpu clock note the port pins become high impedance, except for p130, which is set to low-level output. remark for the reset timing of the power-on-clear circuit and low-voltage detector, see chapter 24 power- on-clear circuit and chapter 25 low-voltage detector .
chapter 22 reset function preliminary user ? s manual u15947ej1v1ud 462 table 22-1. hardware statuses after reset (1/3) hardware status after reset program counter (pc) note 1 the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p7, p12 to p14) (output latches) 00h port mode registers (pm0, pm1, pm3 to pm7, pm12, pm14) ffh pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu14) 00h input switch control register (isc) 00h internal memory size switching register (ims) cfh internal expansion ram size switching register (ixs) 0ch memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h processor clock control register (pcc) 00h ring-osc mode register (rcm) 00h main clock mode register (mcm) 00h main osc control register (moc) 00h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counters 00, 01 (tm00, tm01) 0000h capture/compare registers 000, 010, 001, 011 (cr000, cr010, cr001, cr011) 0000h mode control registers 00, 01 (tmc00, tmc01) 00h prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h 16-bit timer/event counters 00, 01 note 3 timer output control registers 00, 01 (toc00, toc01) 00h timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection registers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 4 00h watch timer operation mode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. 16-bit timer/event counter 01 is available only for the pd780146, 780148, and 78f0148. 4. 8-bit timer h1 only.
chapter 22 reset function preliminary user ? s manual u15947ej1v1ud 463 table 22-1. hardware statuses after reset (2/3) hardware status after reset mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result register (adcr) undefined mode register (adm) 00h analog input channel specification register (ads) 00h power-fail comparison mode register (pfm) 00h a/d converter power-fail comparison threshold register (pft) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface operation mode register 0 (asim0) 01h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface operation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmission status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh serial interface uart6 asynchronous serial interface control register 6 (asicl6) 16h transmit buffer registers 10, 11 (sotb10, sotb11) undefined serial i/o shift registers 10, 11 (sio10, sio11) undefined serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi11 note serial clock selection registers 10, 11 (csic10, csic11) 00h shift register 0 (sioa0) 00h operation mode specification register 0 (csima0) 00h status register 0 (csis0) 00h trigger register 0 (csit0) 00h divisor selection register 0 (brgca0) 03h automatic data transfer address point specification register 0 (adtp0) 00h automatic data transfer interval specification register 0 (adti0) 00h serial interface csia0 automatic data transfer address count register 0 (adtc0) 00h remainder data register 0 (sdr0) 0000h multiplication/division data register a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider multiplier/divider control register 0 (dmuc0) 00h key interrupt key return mode register (krm) 00h clock monitor mode register (clm) 00h note serial interface csi11 is available only for the pd780146, 780148, and 78f0148.
chapter 22 reset function preliminary user ? s manual u15947ej1v1ud 464 table 22-1. hardware statuses after reset (3/3) hardware status after reset reset function reset control flag register (resf) 00h note low-voltage detection register (lvim) 00h note low-voltage detector low-voltage detection level selection register (lvis) 00h note request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l, 1h (mk0l, mk0h, mk1l, mk1h) ffh priority specification flag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h note these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by clm reset by lvi resf see table 22-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) cleared (00h) held
chapter 22 reset function preliminary user ? s manual u15947ej1v1ud 465 22.1 register for confirming reset source many internal reset generation sources exist in the 78k0/kf1 series. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc) circuit, and reading resf clear resf to 00h. figure 22-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol76543210 resf 0 0 0 wdtrf 0 0 clmrf lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. clmrf internal reset request by clock monitor (clm) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bit memory manipulation instruction. the status of resf when a reset request is generated is shown in table 22-2. table 22-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by clm reset by lvi wdtrf set (1) held held clmrf held set (1) held lvirf cleared (0) cleared (0) held held set (1)
preliminary user?s manual u15947ej1v1ud 466 chapter 23 clock monitor 23.1 functions of clock monitor the clock monitor samples the x1 input clock using the on-chip ring-osc, and generates an internal reset signal when the x1 input clock is stopped. when a reset signal is generated by the clock monitor, bit 1 (clmrf) of the reset control flag register (resf) is set to 1. for details of resf, refer to chapter 22 reset function . the clock monitor automatically stops under the following conditions. ? in stop mode and during the oscillation stabilization time ? when the x1 input clock is stopped by software (mstop = 1 or mcc = 1) ? during the oscillation stabilization time after reset is released ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) 23.2 configuration of clock monitor clock monitor consists of the following hardware. table 23-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 23-1. block diagram of clock monitor x1 input clock ring-osc clock internal reset signal enable/disable clme clock monitor mode register (clm)
chapter 23 clock monitor preliminary user ? s manual u15947ej1v1ud 467 23.3 registers controlling clock monitor clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register sets the operation mode of the clock monitor. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 23-2. format of clock monitor mode register (clm) 7 0 clme 0 1 symbol clm address: ffa9h after reset: 00h r/w 6 0 disables clock monitor operation enables clock monitor operation 5 0 4 0 3 0 enables/disables clock monitor operation 2 0 1 0 0 clme cautions 1. once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by reset input or the internal reset signal. 2. if the reset signal is generated by the clock monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control flag register (resf) is set to 1. clmrf is read by software and then automatically cleared to 0. clmrf is cleared under the following conditions. ? ? ? ? reset input ? ? ? ? internal reset signal generation by poc ? ? ? ? after read by software
chapter 23 clock monitor preliminary user ? s manual u15947ej1v1ud 468 23.4 operation of clock monitor this section explains the functions of the clock monitor. the start and stop conditions are as follows. when bit 0 (clme) of the clock monitor mode register (clm) is set to operation enabled (1). ? in stop mode and during the oscillation stabilization time ? during the oscillation stabilization time after reset is released ? when the x1 input clock is stopped by software (mstop = 1 or mcc = 1) ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) table 23-2. operation status of clock monitor (when clme = 1) cpu operation clock operation mode x1 input clock status ring-osc clock status clock monitor status oscillating stop mode stopped stopped note oscillating reset input stopped note stopped oscillating operating x1 input clock halt mode oscillating stopped note stopped stop mode reset input stopped oscillating stopped oscillating operating ring-osc clock halt mode stopped stopped note the ring-osc clock is stopped only when the ? ring-osc can be stopped by software ? is selected by a mask option. if ? ring-osc cannot be stopped ? is selected, the ring-osc clock cannot be stopped. the clock monitor timing is as shown in figure 23-3.
chapter 23 clock monitor preliminary user ? s manual u15947ej1v1ud 469 figure 23-3. timing of clock monitor (1/3) (1) when internal reset is executed by oscillation stop of x1 input clock 4 clocks of ring-osc clock x1 input clock ring-osc clock internal reset signal clme clmrf note note clmrf is read by software and then automatically cleared to 0. clmrf is cleared under the following conditions. ? reset input ? internal reset signal generation by poc ? after read by software (2) clock monitor status after stop mode is released (clme = 1 is set when cpu clock operates on x1 input clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring clme ring-osc clock x1 input clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time.
chapter 23 clock monitor preliminary user ? s manual u15947ej1v1ud 470 figure 23-3. timing of clock monitor (2/3) (3) clock monitor status after stop mode is released (clme = 1 is set when cpu clock operates on ring-osc clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring stopped monitoring clme ring-osc clock x1 input clock cpu operation normal operation 17 clocks clock supply stopped normal operation (ring-osc clock) oscillation stopped oscillation stabilization time (set by osts register) stop when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. (4) clock monitor status after reset input (clme = 1 is set after reset input and during x1 input clock oscillation stabilization time) cpu operation clock monitor status clme ring-osc clock x1 input clock reset oscillation stopped oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring waiting for end of oscillation stabilization time oscillation stopped 17 clocks set to 1 by software reset reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. even if clme is set to 1 by software during the oscillation stabilization time of the x1 input clock, monitoring is not performed until the oscillation stabilization time of the x1 input clock ends. monitoring is automatically started at the end of the oscillation stabilization time.
chapter 23 clock monitor preliminary user ? s manual u15947ej1v1ud 471 figure 23-3. timing of clock monitor (3/3) (5) clock monitor status after reset input (clme = 1 is set after reset input and at the end of x1 input clock oscillation stabilization time) cpu operation clock monitor status clme reset ring-osc clock x1 input clock reset oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring 17 clocks set to 1 by software reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. when clme is set to 1 by software at the end of the oscillation stabilization time of the x1 input clock, monitoring is started.
preliminary user?s manual u15947ej1v1ud 472 chapter 24 power-on-clear circuit 24.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. ? compares supply voltage (v dd ) and detection voltage (v poc ), and generates internal reset signal when v dd < v poc . ? the following can be selected by a mask option. ? poc disabled ? poc used (detection voltage: v poc = 2.85 v 0.15 v) ? poc used (detection voltage: v poc = 3.5 v 0.2 v) caution if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. remark this product incorporates multiple hardware functions that generate an internal reset signal. a flag that indicates the reset cause is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt), low-voltage-detection (lvi) circuit, or clock monitor. resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt, lvi, or the clock monitor. for details of the resf, refer to chapter 22 reset function .
chapter 24 power-on-clear circuit preliminary user?s manual u15947ej1v1ud 473 24.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 24-1. figure 24-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc ) internal reset signal v dd v dd 24.3 operation of power-on-clear circuit in the power-on-clear circuit, the supply voltage (v dd ) and detection voltage (v poc ) are compared, and when v dd < v poc , an internal reset signal is generated. figure 24-2. timing of internal reset signal generation in power-on-clear circuit time supply voltage (v dd ) poc detection voltage (v poc ) 2.7 v internal reset signal
chapter 24 power-on-clear circuit preliminary user ? s manual u15947ej1v0ud 474 24.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. figure 24-3. example of software processing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of poc detection voltage yes power-on-clear ; the ring-osc clock is set as the cpu clock when the reset signal is generated ; the cause of reset (power-on-clear, wdt, lvi, or clock monitor) can be identified by the resf register. ; change the cpu clock from the ring-osc clock to the x1 input clock. ; check the stabilization of oscillation of the x1 input clock by using the ostc register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the ring-osc clock. source: f r (240 khz)/2 7 compare 100 = 53 ms (f r : ring-osc clock oscillation frequency) no note 1 reset checking cause of reset note 2 check stabilization of oscillation change cpu clock 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period, initialization processing is not started. 2. a flowchart is shown on the next page.
chapter 24 power-on-clear circuit preliminary user ? s manual u15947ej1v1ud 475 figure 24-3. example of software processing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no no wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes yes
preliminary user?s manual u15947ej1v1ud 476 chapter 25 low-voltage detector 25.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . ? detection levels (five levels) of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, refer to chapter 22 reset function . 25.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown below. figure 25-1. block diagram of low-voltage detector lvis1 lvis0 lvion lvie ? + detection voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvimd lvif internal reset signal 3 low-voltage detection level selector selector
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 477 25.3 registers controlling low-voltage detector the low-voltage detector is controlled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) (1) low-voltage detection register (lvim) this register sets low-voltage detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 478 figure 25-2. format of low-voltage detection register (lvim) 0 lvif 1 lvimd 2 0 3 0 4 lvie 5 0 6 0 7 lvion symbol lvim address: ffbeh after reset: 00h r/w lvion notes 1, 2 enables low-voltage detection operation 0 disables operation 1 enables operation lvie notes 1, 3, 4 specifies reference voltage generator 0 disables operation 1 enables operation lvimd note 1 low-voltage detection operation mode selection 0 generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 5 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. lvion, lvie, and lvimd are cleared to 0 at a reset other than an lvi reset. these are not cleared to 0 at an lvi reset. 2. when lvion is set to 1, operation of the comparator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 3. when lvie is set to 1, a reference voltage generator operation in the lvi circuit is started. use software to instigate a wait of at least 2 ms from when lvie is set to 1 until lvion is set to 1. 4. if ? use poc ? is selected by a mask option, leave lvie as 0. a wait time (2 ms) until lvion is set to 1 is not necessary. 5. the value of lvif is output as the interrupt request signal intlvi when lvion = 1 and lvimd = 0. caution to stop lvi, follow either of the procedures below. ? ? ? ? when using 8-bit manipulation instruction: write 00h to lvim. ? ? ? ? when using 1-bit memory manipulation instruction: clear lvion to 0 first and then clear lvie to 0.
chapter 25 low-voltage detector preliminary user?s manual u15947ej1v1ud 479 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. figure 25-3. format of low-voltage detection level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 0 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis2 lvis1 lvis0 detection level 000 v lvi0 (4.3 v 0.2 v) 001 v lvi1 (4.1 v 0.2 v) 010 v lvi2 (3.9 v 0.2 v) 011 v lvi3 (3.7 v 0.2 v) 100 v lvi4 (3.5 v 0.2 v) note 101 v lvi5 (3.3 v 0.15 v) note 110 v lvi6 (3.1 v 0.15 v) note 1 1 1 setting prohibited note when the detection voltage of the poc circuit is specified as v poc = 3.5 v 0.2 v by a mask option, do not select v lvi4 to v lvi6 as the lvi detection voltage. even if v lvi4 to v lvi6 are selected, poc circuit has priority.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 480 25.4 operation of low-voltage detector the low-voltage detector can be used in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection register (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> confirm that ? supply voltage (v dd ) > detection voltage (v lvi ) ? at bit 0 (lvif) of lvim. <8> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. 2. if "use poc" is selected by a mask option, procedures <3> and <4> are not required. 3. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following procedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0, lvion to 0, and lvie to 0 in that order.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 481 figure 25-4. timing of low-voltage detector internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v lvif flag lvirf flag note lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared not cleared not cleared cleared by software <2> <1> <5> <7> <8> time clear clear clear clear <3> <4> 2 ms or longer <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) lvimd flag (set by software) note lvirf is bit 0 of the reset control flag register (resf). for details of resf, refer to chapter 22 reset function . remark <1> to <8> in figure 25-4 above correspond to <1> to <8> in the description of ? when starting operation ? in 25.4 (1) when used as reset .
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 482 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection register (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> confirm that ? supply voltage (v dd ) > detection voltage (v lvi ) ? at bit 0 (lvif) of lvim. <8> clear the interrupt request flag of lvi (lviif) to 0. <9> release the interrupt mask flag of lvi (lvimk). <10> execute the ei instruction (when vector interrupts are used). caution if ?use poc? is selected by a mask option, procedures <3> and <4> are not required. ? when stopping operation either of the following procedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0 first, and then clear lvie to 0.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 483 figure 25-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v time lvif flag intlvi lviif flag internal reset signal <2> <1> <5> <7> <8> cleared by software <3> <4> 2 ms or longer <9> cleared by software <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) remark <1> to <9> in figure 25-5 above correspond to <1> to <9> in the description of ? when starting operation ? in 25.4 (2) when used as interrupt .
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 484 25.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (2) below. in this system, take the following actions. (1) when used as reset after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 485 figure 25-6. example of software processing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage yes lvi ; the ring-osc clock is set as the cpu clock when the reset signal is generated ; the cause of reset (power-on-clear, wdt, lvi, or clock monitor) can be identified by the resf register. ; change the cpu clock from the ring-osc clock to the x1 input clock. ; check the stabilization of oscillation of the x1 input clock by using the ostc register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the ring-osc clock. source: f r (240 khz)/2 7 compare 100 = 53 ms (f r : ring-osc clock oscillation frequency) no note 1 reset checking cause of reset note 2 check stabilization of oscillation change cpu clock 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period, initialization processing is not started. 2. a flowchart is shown on the next page.
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 486 figure 25-6. example of software processing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no yes wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes no
chapter 25 low-voltage detector preliminary user ? s manual u15947ej1v1ud 487 (2) when used as interrupt disable interrupts (di) in the servicing routine of the lvi interrupt, and check to see if ? supply voltage (v dd ) > detection voltage (v lvi ) ? , by using bit 0 (lvif) of the low-voltage detection register (lvim). then enable interrupts (ei). in a system where the supply voltage fluctuation period is long in the vicinity of the lvi detection voltage, disable interrupts (di), wait for the supply voltage fluctuation period, check that ? supply voltage (v dd ) > detection voltage (v lvi ) ? with the lvif flag, and then enable interrupts (ei). figure 25-7. example of software processing of lvi interrupt ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check that supply voltage (v dd ) > detection voltage (v lvi ). ; tmifh1 = 1: interrupt request is generated ; enable interrupts. ; disable interrupts. yes no lvif1 of lvim register = 0? yes no 50 ms has passed? (tmifh1 = 1?) lvi lvi interrupt start timer (set to 50 ms) ei di lvi interrupt servicing
preliminary user?s manual u15947ej1v1ud 488 chapter 26 regulator 26.1 outline of regulator the 78k0/kf1 series includes a circuit to realize low-voltage operation inside the device. to stabilize the regulator output voltage, connect the regc pin to v ss via a 0.1 f capacitor. the regulator of the 78k0/kf1 series stops operating in the following cases. ? during the reset period ? in stop mode ? in halt mode when the cpu is operating on the subsystem clock figure 26-1 shows the block diagram of the periphery of the regulator. figure 26-1. block diagram of regulator periphery ev dd system i/o buffer internal digital circuits bidirectional level shifter a/d converter flash memory ( pd78f0148 only) regulator x1, ring, sub oscillator v dd regc v pp 0.1 f av ref ev dd remark to use the cpu at high speed (f xp = 10 mhz, v dd = 4.0 to 5.5 v), connect the regc pin directly to v dd and use at the same potential as the v dd pin.
preliminary user?s manual u15947ej1v1ud 489 chapter 27 mask options mask rom versions are provided with the following mask options. 1. power-on-clear (poc) circuit ? poc cannot be used ? poc used (detection voltage: v poc = 2.85 v 0.15 v) ? poc used (detection voltage: v poc = 3.5 v 0.2 v) 2. ring-osc ? cannot be stopped ? can be stopped by software 3. pull-up resistor of p60 to p63 pins ? pull-up resistor can be incorporated in 1-bit units (pull-up resistors are not available for the flash memory versions.) flash memory versions that support the mask options of the mask rom versions are as follows. table 27-1. flash memory versions supporting mask options of mask rom versions mask option poc circuit ring-osc flash memory version cannot be stopped pd78f0148m1 poc cannot be used can be stopped by software pd78f0148m2 cannot be stopped pd78f0148m3 poc used (v poc = 2.85 v 0.15 v) can be stopped by software pd78f0148m4 cannot be stopped pd78f0148m5 poc used (v poc = 3.5 v 0.2 v) can be stopped by software pd78f0148m6
preliminary user?s manual u15947ej1v1ud 490 chapter 28 pd78f0148 the pd78f0148 is provided as the flash memory version of the 78k0/kf1 series. the pd78f0148 replaces the internal mask rom of the pd780148 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. table 28-1 lists the differences between the pd78f0148 and the mask rom versions. table 28-1. differences between pd78f0148 and mask rom versions item pd78f0148 mask rom versions internal rom configuration flash memory mask rom internal rom capacity 60 kb note pd780143: 24 kb pd780144: 32 kb pd780146: 48 kb pd780148: 60 kb internal expansion ram capacity 1024 bytes note pd780143: none pd780144: none pd780146: 1024 bytes pd780148: 1024 bytes ic pin none available v pp pin available none electrical specifications refer to chapter 30 electrical specifications (target values) . note the same capacity as the mask rom versions can be specified by means of the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions.
chapter 28 pd78f0148 preliminary user?s manual u15947ej1v1ud 491 28.1 internal memory size switching register the pd78f0148 allows users to select the internal memory capacity using the internal memory size switching register (ims) so that the same memory map as that of the mask rom versions with a different internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution be sure to set the value of the relevant mask rom version at initialization. figure 28-1. format of internal memory size switching register (ims) address: fff0h after reset: cfh r/w symbol76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 011024 kb 100032 kb 110048 kb 111160 kb other than above setting prohibited the ims settings required to obtain the same memory map as mask rom versions are shown in table 28-2. table 28-2. internal memory size switching register settings target mask rom versions ims setting pd780143 c6h pd780144 c8h pd780146 cch pd780148 cfh caution when using a mask rom version, be sure to set the value indicated in table 28-2 to ims.
chapter 28 pd78f0148 preliminary user?s manual u15947ej1v1ud 492 28.2 internal expansion ram size switching register this register is used to set the internal expansion ram capacity via software. this register is set by an 8-bit memory manipulation instruction. reset input sets ixs to 0ch. caution be sure to set the value of the relevant mask rom version at initialization. figure 28-2. format of internal expansion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol76543210 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 0 1 1 0 0 0 bytes 0 1 0 1 0 1024 bytes other than above setting prohibited the ixs settings required to obtain the same memory map as mask rom versions are shown in table 28-3. table 28-3. internal expansion ram size switching register settings target mask rom versions ixs setting pd780143 0ch pd780144 0ch pd780146 0ah pd780148 0ah caution when using a mask rom version, be sure to set the value indicated in table 28-3 to ixs.
chapter 28 pd78f0148 preliminary user?s manual u15947ej1v1ud 493 28.3 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is performed after connecting a dedicated flash programmer (flashpro iii (fl-pr3, pg-fp3)) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro iii. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 28.3.1 selection of communication mode writing to flash memory is performed using flashpro iii and serial communication. select the communication mode for writing from table 28-4. for the selection of the communication mode, a format like the one shown in figure 28-3 is used. the communication mode is selected according to the number of v pp pulses shown in table 28-4. table 28-4. communication mode list communication mode number of channels pin used note number of v pp pulses sck10/txd0/p10 si10/rxd0/p11 so10/p12 0 3-wire serial i/o 1 sck10/txd0/p10 si10/rxd0/p11 so10/p12 hs/p15/toh0 3 txd0/sck10/p10 rxd0/si10/p11 8 uart (uart0) 1 txd0/sck10/p10 rxd0/si10/p11 hs/p15/toh0 11 uart (uart6) 1 txd6/p13 rxd6/p14 9 note after shifting to flash memory programming mode, all pins not used for flash memory programming are set to the same state as after reset. therefore, since all ports become output high-impedance, pin processing, such as connecting to v dd or v ss via a resistor is required if the output high-impedance state is not acknowledged by external devices. caution be sure to select the number of v pp pulses shown in table 28-4 for the communication mode.
chapter 28 pd78f0148 preliminary user?s manual u15947ej1v1ud 494 figure 28-3. communication mode selection format 10 v v pp reset v dd v ss v dd v ss v pp pulses flash memory write mode 28.3.2 flash memory programming function flash memory writing is performed via command and data transmit/receive operations using the selected communication mode. the main functions are listed in table 28-5. table 28-5. main functions of flash memory programming function description reset used to detect write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch erase erases the entire memory contents. batch blank check checks the erase status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs successive write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. delete time setting inputs the memory delete time. baud rate setting sets the communication rate when the uart method is used. silicon signature read outputs the device name, memory capacity, and device block information.
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 495 28.3.3 connecting flashpro iii the connection between flashpro iii and the pd78f0148 differs depending on the communication mode (3-wire serial i/o or uart). figures 28-4 to 28-8 show the connection diagrams of each case. figure 28-4. connection of flashpro iii in 3-wire serial i/o mode vpp vdd reset sck so si gnd v pp v dd / av ref reset sck10 si10 so10 v ss / av ss flashpro iii pd78f0148 figure 28-5. connection of flashpro iii in 3-wire serial i/o mode (using handshake) vpp vdd reset sck so si gnd v pp v dd / av ref reset sck10 si10 so10 hs hs (p15) v ss / av ss flashpro iii pd78f0148
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 496 figure 28-6. connection of flashpro iii in uart (uart0) mode vpp vdd reset so si gnd v pp v dd / av ref reset rxd0 txd0 v ss / av ss flashpro iii pd78f0148 figure 28-7. connection of flashpro iii in uart (uart0) mode (using handshake) vpp vdd reset so si gnd v pp v dd / av ref reset rxd0 txd0 hs hs (p15) v ss / av ss flashpro iii pd78f0148 figure 28-8. connection of flashpro iii in uart (uart6) mode vpp vdd reset so si gnd v pp v dd / av ref reset rxd6 txd6 v ss / av ss flashpro iii pd78f0148
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 497 28.3.4 connection on adapter for flash memory writing examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 28-9. example of wiring adapter for flash memory writing in 3-wire serial i/o mode pd78f0148 gnd vdd lvdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 498 figure 28-10. example of wiring adapter for flash memory writing in 3-wire serial i/o mode (using handshake) pd78f0148 gnd vdd lvdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 499 figure 28-11. example of wiring adapter for flash memory writing in uart (uart0) mode pd78f0148 gnd vdd lvdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 500 figure 28-12. example of wiring adapter for flash memory writing in uart (uart0) mode (using handshake) pd78f0148 gnd vdd lvdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
chapter 28 pd78f0148 preliminary user ? s manual u15947ej1v1ud 501 figure 28-13. example of wiring adapter for flash memory writing in uart (uart6) mode pd78f0148 gnd vdd lvdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
preliminary user?s manual u15947ej1v1ud 502 chapter 29 instruction set this chapter lists each instruction set of the 78k0/kf1 series in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 29.1 conventions used in operation list 29.1.1 operand identifiers and specification methods operands are written in the ?operand? column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more methods, select one of them. uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 29-1. operand identifiers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, refer to table 3-5 special function register list .
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 503 29.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 29.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 504 29.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 12 ? a r r, a note 3 12 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) mov [hl + c], a 1 6 7 + m (hl + c) a a, r note 3 12 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 505 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 14 ? ax rp rp, ax note 3 14 ? rp ax ax, !addr16 3 10 12 + 2n ax (addr16) movw !addr16, ax 3 10 12 + 2m (addr16) ax 16-bit data transfer xchw ax, rp note 3 14 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 24 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) add a, [hl + c] 2 8 9 + n a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 24 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 506 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 24 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 + n a, cy a ? (addr16) a, [hl] 1 4 5 + n a, cy a ? (hl) a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 24 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 + n a, cy a ? (addr16) ? cy a, [hl] 1 4 5 + n a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) 8-bit operation and a, [hl + c] 2 8 9 + n a a (hl + c) notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 507 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) or a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) xor a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 24 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 + n a ? (addr16) a, [hl] 1 4 5 + n a ? (hl) a, [hl + byte] 2 8 9 + n a ? (hl + byte) a, [hl + b] 2 8 9 + n a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 + n a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 508 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x216 ? ax a x multiply/ divide divuw c225 ? ax (quotient), c (remainder) ax c r12 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r12 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 24 ? decimal adjust accumulator after addition bcd adjustment adjbs 24 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 509 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 + n + m (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 510 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 brk 16 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 16 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr call/return retb 16 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 rrr pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pc h a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 511 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 12 ? no operation ei 2 ? 6ie 1 (enable interrupt) di 2 ? 6ie 0 (disable interrupt) halt 26 ? set halt mode cpu control stop 26 ? set stop mode notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 512 29.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except r = a
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 513 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1
chapter 29 instruction set preliminary user?s manual u15947ej1v1ud 514 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
preliminary user?s manual u15947ej1v1ud 515 chapter 30 electrical specifications (target values) these specifications are only target values, and may not be satisfied by mass-produced products. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v ev dd ? 0.3 to +6.5 v regc ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v ev ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0148 only note 2 ? 0.3 to +10.5 v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p120, p140 to p145, x1, x2, xt1, xt2, reset ? 0.3 to v dd + 0.3 note 1 v n-ch open drain ? 0.3 to +13 v v i2 p62, p63 on-chip pull-up resistor ? 0.3 to v dd + 0.3 note 1 v input voltage v i3 v pp in flash programming mode ( pd78f0148 only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 10 ma p00 to p06, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p142 to p145 ? 30 ma output current, high i oh total of all pins ? 60 ma p10 to p17, p30 to p33, p120, p130, p140, p141 ? 30 ma note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 30 electrical specifications (target values) preliminary user?s manual u15947ej1v1ud 516 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 20 ma per pin p60 to p63 30 ma p00 to p06, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p142 to p145 35 ma output current, low i ol total of all pins 70 ma p10 to p17, p30 to p33, p62, p63, p120, p130, p140, p141 35 ma operating ambient temperature t a in normal operation mode ? 40 to +85 c pd780143, 780144, 780146, 780148 ? 65 to +150 storage temperature t stg pd78f0148 ? 40 to +125 c note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? ? ? ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (15 s if the supply voltage is dropped by the regulator) (see a in the figure below). ? ? ? ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 517 x1 oscillator characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 3.3 v v dd < 5.5 v 2.0 8.38 when a capacitor is connected to the regc pin note 2 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 ceramic resonator c1 x2 x1 ic (v pp ) c2 oscillation frequency (f xp ) note 1 when the regc pin is directly connected to v dd 2.7 v v dd < 3.3 v 2.0 5.0 mhz 3.3 v v dd < 5.5 v 2.0 8.38 when a capacitor is connected to the regc pin note 2 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 crystal resonator c1 x2 x1 ic (v pp ) c2 oscillation frequency (f xp ) note 1 when the regc pin is directly connected to v dd 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 x1 input frequency (f xp ) note 1 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 46 500 3.3 v v dd < 4.0 v 56 500 external clock note 3 x2 x1 x1 input high- /low-level width (t xph , t xpl ) 2.7 v v dd < 3.3 v 96 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. when the regc pin is connected to v ss via a 0.1 f capacitor. 3. connect the regc pin directly to v dd . cautions 1. when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check the oscillation stabilization time of the x1 input clock using the oscillation stabilization time status register (ostc). determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 518 ring-osc oscillator characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 480 khz subsystem clock oscillator characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 ic (v pp ) xt2 c4 c3 rd oscillation frequency (f xt ) note 32 32.768 35 khz xt1 input frequency (f xt ) note 32 38.5 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 12 15 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 519 dc characteristics (1/4) (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin 4.0 v v dd 5.5 v ? 5ma total of p10 to p17, p30 to p33, p120, p130, p140, p141 4.0 v v dd 5.5 v ? 25 ma total of p00 to p06, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p142 to p145 4.0 v v dd 5.5 v ? 25 ma output current, high i oh all pins 2.7 v v dd < 4.0 v ? 10 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 4.0 v v dd 5.5 v 10 ma per pin for p60 to p63 4.0 v v dd 5.5 v 15 ma total of p10 to p17, p30 to p33, p62, p63, p120, p130, p140, p141 4.0 v v dd 5.5 v 30 ma total of p00 to p06, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p142 to p145 4.0 v v dd 5.5 v 30 ma output current, low i ol all pins 2.7 v v dd < 4.0 v 10 ma v ih1 p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p144, p145 0.7v dd v dd v v ih2 p00 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, reset 0.8v dd v dd v v ih3 p20 to p27 note 0.7av ref av ref v v ih4 p60, p61 0.7v dd v dd v v ih5 p62, p63 0.7v dd 12 v input voltage, high v ih6 x1, x2, xt1, xt2 v dd ? 0.5 v dd v v il1 p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p144, p145 00.3v dd v v il2 p00 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, reset 00.2v dd v v il3 p20 to p27 note 0 0.3av ref v v il4 p60, p61 0 0.3v dd v v il5 p62, p63 0 0.3v dd v input voltage, low v il6 x1, x2, xt1, xt2 0 0.4 v note when used as a/d converter analog input pins, set av ref = v dd . remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 520 dc characteristics (2/4) (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit total of p10 to p17, p30 to p33, p120, p130, p140, p141 i oh = ? 25 ma 4.0 v v dd 5.5 v, i oh = ? 5 ma v dd ? 1.0 v total of p00 to p06, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p142 to p145 i oh = ? 25 ma 4.0 v v dd 5.5 v, i oh = ? 5 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 2.7 v v dd < 4.0 v v dd ? 0.5 v total of p10 to p17, p30 to p33, p62, p63, p120, p130, p140, p141 i ol = 30 ma 4.0 v v dd 5.5 v, i ol = 10 ma 1.3 v total of p00 to p06, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p142 to p145 i ol = 30 ma 4.0 v v dd 5.5 v, i ol = 10 ma 1.3 v v ol1 i ol = 400 a 2.7 v v dd < 4.0 v 0.4 v output voltage, low v ol2 p60 to p63 i ol = 15 ma 2.0 v v i = v dd p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p120, p140 to p145, reset 3 a i lih1 v i = av ref p20 to p27 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p62, p63 (n-ch open drain) 3 a i lil1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p120, p140 to p145, reset ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v i = 0 v p62, p63 (n-ch open drain) ? 3 note a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a pull-up resistance value r l v i = 0 v 10 30 100 k ? v pp supply voltage ( pd78f0148 only) v pp1 in normal operation mode 0 0.2v dd v note if there is no on-chip pull-up resistor for p62 and p63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to ? 45 a flows during only one cycle. at all other times, the maximum leakage current is ? 3 a. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 521 dc characteristics (3/4): pd78f0148 (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 13.5 29.7 ma f xp = 10 mhz v dd = 5.0 v 10% notes 3, 7 when a/d converter is operating note 9 14.5 31.9 ma when a/d converter is stopped 9.5 19 ma f xp = 8.38 mhz v dd = 5.0 v 10% notes 3, 8 when a/d converter is operating note 9 10.5 21 ma when a/d converter is stopped 5 10 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 5 mhz v dd = 3.0 v 10% note 3 when a/d converter is operating note 9 714ma when peripheral functions are stopped 1.7 3.4 ma f xp = 10 mhz v dd = 5.0 v 10% notes 3, 7 when peripheral functions are operating 9.6 ma when peripheral functions are stopped 12ma f xp = 8.38 mhz v dd = 5.0 v 10% notes 3, 8 when peripheral functions are operating 4.5 ma when peripheral functions are stopped 0.5 1 ma i dd2 x1 crystal oscillation halt mode f xp = 5 mhz v dd = 3.0 v 10% note 3 when peripheral functions are operating 2ma v dd = 5.0 v 10% 0.7 2.1 ma i dd3 ring-osc operating mode note 4 v dd = 3.0 v 10% 0.4 1.2 ma v dd = 5.0 v 10% 115 230 a i dd4 32.768 khz crystal oscillation operating mode notes 4, 6 v dd = 3.0 v 10% 95 190 a v dd = 5.0 v 10% 30 60 a i dd5 32.768 khz crystal oscillation halt mode notes 4, 6 v dd = 3.0 v 10% 6 18 a poc: off, ring: off 0.1 30 a poc: off, ring: on 14 58 a poc: on note 5 , ring: off 3.5 35.5 a v dd = 5.0 v 10% poc: on note 5 , ring: on 17.5 63.5 a poc: off, ring: off 0.05 10 a poc: off, ring: on 7.5 25 a poc: on note 5 , ring: off 3.5 15.5 a supply current note 1 i dd6 stop mode v dd = 3.0 v 10% poc: on note 5 , ring: on 11 30.5 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. when main system clock is stopped. 5. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option. 6. when poc-off (including lvie = 0) is selected by a mask option and ring-osc oscillation is stopped. 7. when the regc pin is directly connected to v dd . 8. when the regc pin is connected to v ss via a 0.1 f capacitor. 9. including the current that flows through the av ref pin.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 522 dc characteristics (4/4): pd780143, 780144, 780146, and 780148 (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 6 15 ma f xp = 10 mhz v dd = 5.0 v 10% notes 3, 7 when a/d converter is operating note 9 7 17.5 ma when a/d converter is stopped 4 8 ma f xp = 8.38 mhz v dd = 5.0 v 10% notes 3, 8 when a/d converter is operating note 9 510ma when a/d converter is stopped 3 6 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 5 mhz v dd = 3.0 v 10% note 3 when a/d converter is operating note 9 48ma when peripheral functions are stopped 1.7 3.4 ma f xp = 10 mhz v dd = 5.0 v 10% notes 3, 7 when peripheral functions are operating 9.6 ma when peripheral functions are stopped 12ma f xp = 8.38 mhz v dd = 5.0 v 10% notes 3, 8 when peripheral functions are operating 4.5 ma when peripheral functions are stopped 0.5 1 ma i dd2 x1 crystal oscillation halt mode f xp = 5 mhz v dd = 3.0 v 10% note 3 when peripheral functions are operating 2ma v dd = 5.0 v 10% 0.3 0.9 ma i dd3 ring-osc operating mode note 4 v dd = 3.0 v 10% 0.19 0.57 ma v dd = 5.0 v 10% 45 90 a i dd4 32.768 khz crystal oscillation operating mode notes 4, 6 v dd = 3.0 v 10% 25 50 a v dd = 5.0 v 10% 30 60 a i dd5 32.768 khz crystal oscillation halt mode notes 4, 6 v dd = 3.0 v 10% 6 18 a poc: off, ring: off 0.1 30 a poc: off, ring: on 14 58 a poc: on note 5 , ring: off 3.5 35.5 a v dd = 5.0 v 10% poc: on note 5 , ring: on 17.5 63.5 a poc: off, ring: off 0.05 10 a poc: off, ring: on 7.5 25 a poc: on note 5 , ring: off 3.5 15.5 a supply current note 1 i dd6 stop mode v dd = 3.0 v 10% poc: on note 5 , ring: on 11 30.5 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. when main system clock is stopped. 5. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option. 6. when poc-off (including lvie = 0) is selected by a mask option and ring-osc oscillation is stopped. 7. when the regc pin is directly connected to v dd . 8. when the regc pin is connected to v ss via a 0.1 f capacitor. 9. including the current that flows through the av ref pin.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 523 ac characteristics (1) basic operation (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 3.3 v v dd 5.5 v 0.238 16 s note 1 2.7 v v dd < 3.3 v 0.4 16 s 4.0 v v dd 5.5 v 0.2 16 s 3.3 v v dd < 4.0 v 0.238 16 s x1 input clock note 2 2.7 v v dd < 3.3 v 0.4 16 s main system clock operation ring-osc clock 4.17 8.33 16.67 s instruction cycle (minimum instruction execution time) t cy subsystem clock operation 114 122 125 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 4 s ti000, ti010, ti001 note 3 , ti011 note 3 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 4 s 4.0 v v dd 5.5 v 10 mhz ti50, ti51 input frequency f ti5 2.7 v v dd < 4.0 v 5 mhz 4.0 v v dd 5.5 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 2.7 v v dd < 4.0 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s 4.0 v v dd 5.5 v 50 ns key return input low-level width t kr 2.7 v v dd < 4.0 v 100 ns reset low-level width t rst 10 s notes 1. when the regc pin is connected to v ss via a 0.1 f capacitor. 2. when the regc pin is directly connected to v dd . 3. pd780146, 780148, and 78f0148 only. 4. selection of f sam = f xp , f xp /4, f xp /256, or f xp , f xp /16, f xp /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode registers 00 and 01 (prm00, prm01). note that when selecting the ti000, ti010, ti001, or ti011 valid edge as the count clock, f sam = f xp.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 524 t cy vs. v dd (x1 input clock operation) (a) when regc pin is connected to v ss via 0.1 f capacitor 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 3.3 guaranteed operation range 20.0 16.0 0.238 (b) when regc pin is directly connected to v dd 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 3.3 guaranteed operation range 20.0 16.0 0.238
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 525 (2) read/write operation (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) (1/2) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns t add1 (2 + 2n)t cy ? 54 ns data input time from address t add2 (3 + 2n)t cy ? 60 ns address output time from rd t rdad 0 100 ns t rdd1 (2 + 2n)t cy ? 87 ns data input time from rd t rdd2 (3 + 2n)t cy ? 93 ns read data hold time t rdh 0ns t rdl1 (1.5 + 2n)t cy ? 33 ns rd low-level width t rdl2 (2.5 + 2n)t cy ? 33 ns t rdwt1 t cy ? 43 ns input time from rd to wait t rdwt2 t cy ? 43 ns input time from wr to wait t wrwt t cy ? 25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy ? 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy ? 15 ns delay time from rd to astb at external fetch t rdast 0.8t cy ? 15 1.2t cy ns address hold time from rd at external fetch t rdadh 0.8t cy ? 15 1.2t cy + 30 ns write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy ? 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used at 0.238 s (min). remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 526 (2) read/write operation (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) (2/2) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns t add1 (2 + 2n)t cy ? 108 ns input time from address to data t add2 (3 + 2n)t cy ? 120 ns output time from rd to address t rdad 0 200 ns t rdd1 (2 + 2n)t cy ? 148 ns input time from rd to data t rdd2 (3 + 2n)t cy ? 162 ns read data hold time t rdh 0ns t rdl1 (1.5 + 2n)t cy ? 40 ns rd low-level width t rdl2 (2.5 + 2n)t cy ? 40 ns t rdwt1 t cy ? 75 ns input time from rd to wait t rdwt2 t cy ? 60 ns input time from wr to wait t wrwt t cy ? 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy ? 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy ? 30 ns delay time from rd to astb at external fetch t rdast 0.8t cy ? 30 1.2t cy ns hold time from rd to address at external fetch t rdadh 0.8t cy ? 30 1.2t cy + 60 ns write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy ? 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used at 0.4 s (min). remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 527 (3) serial interface (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbs (b) uart mode (uart0, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbs (c) 3-wire serial i/o mode (master mode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 3.3 v v dd < 4.0 v 240 ns sck1n cycle time t kcy1 2.7 v v dd < 3.3 v 400 ns sck1n high-/low-level width t kh1 , t kl1 t kcy1 /2 ? 10 ns si1n setup time (to sck1n )t sik1 30 ns si1n hold time (from sck1n )t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 100 pf note 30 ns note c is the load capacitance of the sck1n and so1n output lines. (d) 3-wire serial i/o mode (slave mode, sck1n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n )t sik2 80 ns si1n hold time (from sck1n )t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 100 pf note 120 ns note c is the load capacitance of the so1n output line. remark n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 528 (e) 3-wire serial i/o mode with automatic transmit/receive function (scka0... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy3 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v t kcy3 2 ? 50 ns scka0 high-/low-level width t th3 , t tl3 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns sia0 setup time (to scka0 )t sik3 100 ns sia0 hold time (from scka0 )t ksi3 300 ns 4.0 v v dd 5.5 v 200 delay time from scka0 to soa0 output t kso3 c = 100 pf note 2.7 v v dd < 4.0 v 300 ns time from scka0 to stb0 t sbd t kcy3 /2 ? 100 ns 4.0 v v dd 5.5 v t kcy3 ? 30 ns strobe signal high-level width t sbw 2.7 v v dd < 4.0 v t kcy3 ? 60 ns busy signal setup time (to busy signal detection timing) t bys 100 ns 4.0 v v dd 5.5 v 100 ns busy signal hold time (from busy signal detection timing) t byh 2.7 v v dd < 4.0 v 150 ns time from busy inactive to scka0 t sps 2t kcy3 ns note c is the load capacitance of the scka0 and soa0 output lines. (f) 3-wire serial i/o mode with automatic transmit/receive function (scka0 ... external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy4 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v 300 ns scka0 high-/low-level width t kh4 , t kl4 2.7 v v dd < 4.0 v 600 ns sia0 setup time (to scka0 )t sik4 100 ns sia0 hold time (from scka0 )t ksi4 300 ns 4.0 v v dd 5.5 v 200 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 2.7 v v dd < 4.0 v 300 ns when external device expansion function is used 120 ns scka0 rise/fall time t r4 , t f4 when external device expansion function is not used 1000 ns note c is the load capacitance of the soa0 output line.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 529 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note pd780146, 780148, and 78f0148 only.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 530 reset input timing reset t rsl read/write operation external fetch (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 531 external data access (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 532 serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0: pd780143, 780144 n = 0, 1: pd780146, 780148, 78f0148
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 533 3-wire serial i/o mode with automatic transmit/receive function: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t byh t sps t bys 789 note 10 note 10+n note 1 scka0 busy0 (active-high) note the signal is not actually driven low here; it is shown as such to indicate the timing.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 534 a/d converter characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.4 %fsr overall error notes 1, 2 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 4.0 v av ref 5.5 v 14 100 s conversion time t conv 2.7 v av ref < 4.0 v 17 100 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. poc circuit characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v poc0 mask option = 3.5 v 3.3 3.5 3.7 v detection voltage v poc1 mask option = 2.85 v 2.7 2.85 3.0 v v dd : 0 v 2.7 v 0.0015 1500 ms power supply rise time t pth v dd : 0 v 3.3 v 0.002 1800 ms response delay time 1 note t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note t pd when power supply falls, v dd = 1.7 v 1.0 ms minimum pulse width t pw 0.2 ms note time required from voltage detection to reset release. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 535 lvi circuit characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.5 v v lvi1 3.9 4.1 4.3 v v lvi2 3.7 3.9 4.1 v v lvi3 3.5 3.7 3.9 v v lvi4 3.3 3.5 3.7 v v lvi5 3.15 3.3 3.45 v detection voltage v lvi6 2.95 3.1 3.25 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time note 2 t lwait0 0.5 2.0 ms operation stabilization wait time note 3 t lwait1 0.1 0.2 ms notes 1. time required from voltage detection to interrupt output or reset output. 2. time required from setting lvie to 1 to reference voltage stabilization when poc = off is selected by the poc mask option. 3. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 2. v pocn < v lvim (n = 0 and 1, m = 0 to 6) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t wait0 t lw t ld t wait1 lvie 1 lvion 1 data memory stop mode low supply voltage data retention characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.6 5.5 v release signal set time t srel 0 s
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 536 flash memory programming characteristics: pd78f0148 (t a = +10 to +60 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xp = 10 mhz, v dd = 5.5 v 37 ma v pp supply current i pp v pp = v pp2 100 ma step erase time note 1 t er 0.199 0.2 0.201 s overall erase time note 2 t era when step erase time = 0.2 s 20 s/chip writeback time note 3 t wb 49.4 50 50.6 ms number of writebacks per 1 writeback command note 4 c wb when writeback time = 50 ms 60 times number of erases/writebacks c erwb 16 times step write time note 5 t wr 48 50 52 s overall write time per word note 6 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ? erase write ? and ? write only ? are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark the range of the operating clock during flash memory programming is the same as the range during normal operation.
chapter 30 electrical specifications (target values) preliminary user ? s manual u15947ej1v1ud 537 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 10 s v pp pulse input start time from reset t rp 2ms v pp pulse high-/low-level width t pw 8 s v pp pulse input end time from reset t rpe 20 ms v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe
preliminary user?s manual u15947ej1v1ud 538 chapter 31 package drawings 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f1.25 14.0 0.2 b 12.0 0.2 m n0.08 0.145 0.05 p q0.1 0.05 1.0 j 0.5 (t.p.) k l0.5 1.0 0.2 i0.08 s1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u0.6 0.15
chapter 31 package drawings preliminary user ? s manual u15947ej1v1ud 539 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
preliminary user?s manual u15947ej1v1ud 540 chapter 32 cautions for wait 32.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflicts with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to table 32-1 ). this must be noted when real-time processing is performed.
chapter 32 cautions for wait preliminary user?s manual u15947ej1v1ud 541 32.2 peripheral hardware that generates wait table 32-1 lists the registers that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 32-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks watchdog timer wdtm write 3 clocks (fixed) serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write pfm write pft write 2 to 5 clocks note (when adm.5 flag = ?1?) 2 to 9 clocks note (when adm.5 flag = ?0?) adcr read 1 to 5 clocks (when adm.5 flag = ?1?) 1 to 9 clocks (when adm.5 flag = ?0?) a/d converter {(1/f macro ) 2/(1/f cpu )} + 1 *the result after the decimal point is truncated if it is less than t cpul after it has been multiplied by (1/f cpu ), and is rounded up if it exceeds t cpul . f macro : macro operating frequency (when bit 5 (fr2) of adm = ?1?: f x /2, when bit 5 (fr2) of adm = ?0?: f x /2 2 ) f cpu : cpu clock frequency t cpul : low-level width of cpu clock note no wait cycle is generated for the cpu if the number of wait clocks calculated by the above expression is 1. remarks 1. the clock is the cpu clock (f cpu ). 2. when the cpu is operating on the subsystem clock and the x1 input clock is stopped, do not access the registers listed above using an access method in which a wait request is issued.
chapter 32 cautions for wait preliminary user?s manual u15947ej1v1ud 542 32.3 example of wait occurrence <1> watchdog timer number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (mov sfr, a).) number of execution clocks: 10 (7 clocks when data is written to a register that does not issue a wait (mov sfr, #byte).) <2> serial interface uart6 number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (mov a, sfr).) <3> a/d converter table 32-2. number of wait clocks and number of execution clocks on occurrence of wait (a/d converter) ? when f x = 10 mhz, t cpul = 50 ns value of bit 5 (fr2) of adm register f cpu number of wait clocks number of execution clocks f x 9 clocks 14 clocks f x /2 5 clocks 10 clocks f x /2 2 3 clocks 8 clocks f x /2 3 2 clocks 7 clocks 0 f x /2 4 0 clocks (1 clock note ) 5 clocks (6 clocks note ) f x 5 clocks 10 clocks f x /2 3 clocks 8 clocks f x /2 2 2 clocks 7 clocks f x /2 3 0 clocks (1 clock note ) 5 clocks (6 clocks note ) 1 f x /2 4 0 clocks (1 clock note ) 5 clocks (6 clocks note ) note on execution of mov a, adcr remark the clock is the cpu clock (f cpu ). f x : x1 input clock frequency t cpul : low-level width of cpu clock
preliminary user?s manual u15947ej1v1ud 543 appendix a development tools the following development tools are available for the development of systems that employ the 78k0/kf1 series. figure a-1 shows the development tool configuration. ? ? ? ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at compatibles. ? ? ? ? windows unless otherwise specified, ?windows? means the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver 4.0
appendix a development tools preliminary user?s manual u15947ej1v1ud 544 figure a-1. development tool configuration system simulator integrated debugger device file embedded software real-time os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer performance board remark the item in the broken-line box differs according to the development environment. see a.4.1 hardware .
appendix a development tools preliminary user?s manual u15947ej1v1ud 545 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
appendix a development tools preliminary user?s manual u15947ej1v1ud 546 a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df780148) (sold separately). this assembler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. ra78k0 assembler package part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an assembler package and device file (both sold separately). this c compiler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. cc78k0 c compiler package part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with a tool (ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0) (all sold separately). the corresponding os and host machine differ depending on the tool to be used. df780148 notes 1, 2 device file part number: s df780148 this is a source file of the functions that configure the object library included in the c compiler package. this file is required to match the object library included in the c compiler package to the user?s specifications. since this is a source file, its working environment does not depend on any particular operating system. cc78k0-l note 3 c library source file part number: s cc78k0-l notes 1. the df780148 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0. 2. under development 3. the cc78k0-l is not included in the software package (sp78k0).
appendix a development tools preliminary user?s manual u15947ej1v1ud 547 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df780148 s cc78k0-l host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4) solaris (rel. 2.5.1) 1/4-inch cgmt a.3 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flash programmer flash programmer dedicated to microcontrollers with on-chip flash memory. fa-80gk-9eu fa-80gc-8bt flash memory writing adapter flash memory writing adapter used connected to the flashpro iii. ? fa-80gk-9eu: for 80-pin plastic tqfp (gk-9eu type) ? fa-80gc-8bt: for 80-pin plastic qfp (gc-8bt type) flashpro iii controller program to control flashpro iii from a pc. provided with flashpro iii. remark fl-pr3, fa-80gk-9eu, and fa-80gc-8bt are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd.
appendix a development tools preliminary user?s manual u15947ej1v1ud 548 a.4 debugging tools a.4.1 hardware ie-78k0-ns in-circuit emulator the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-78k0-ns-pa performance board this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. ie-78k0-ns-a in-circuit emulator product that combines the ie-78k0-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a 100 v to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when using a pc-9800 series computer (except notebook type) as the ie-78k0-ns(-a) host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable required when using a notebook-type computer as the ie-78k0-ns(-a) host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the ie-78k0- ns(-a) host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the ie-78k0-ns(-a) host machine. ie-780148-ns-em1 note emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. np-80gk emulation probe this probe is used to connect the in-circuit emulator to a target system and is designed for use with 80-pin plastic tqfp (gk-9eu type). tgk-080sdw conversion adapter this conversion socket connects the np-80gk to a target system board designed for an 80-pin plastic tqfp (gk-9eu type). np-80gc emulation probe this emulation probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). ev-9200gc-80 conversion socket this conversion socket is used to connect the np-80gc and target system board to which 80-pin plastic qfp (gc-8bt type) can be connected. this emulation probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). np-80gc-tq np-h80gc-tq emulation probe tgc-080sbp conversion adapter this conversion adapter is used to connect the np-80gc-tq or np-h80gc-tq and a target system board to which an 80-pin plastic qfp (gc-8bt type) can be connected. note under development remarks 1. np-80gk, np-80gc, np-80gc-tq, and np-h80gc-tq are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgk-080sdw and tgc-080sbp are products of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) 3. ev-9200gc-80 is sold in five-device units. 4. tgk-080sdw and tgc-080sbp are sold in individual units.
appendix a development tools preliminary user?s manual u15947ej1v1ud 549 a.4.2 software this system simulator is used to perform debugging at c source level or assembler level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in- circuit emulator, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with a device file (df780148) (sold separately). sm78k0 system simulator part number: s sm78k0 this debugger is a control program used to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif tm . it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen at c-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as a task debugger and system performance analyzer, the efficiency of debugging programs that run on real-time oss can be improved. it should be used in combination with a device file (sold separately). id78k0-ns integrated debugger (supporting in-circuit emulator ie-78k0-ns(-a)) part number: s id78k0-ns remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
preliminary user?s manual u15947ej1v1ud 550 appendix b embedded software the following embedded products are available for efficient development and maintenance of the 78k0/kf1 series. real-time os the rx78k/0 is a real-time os conforming to the itron specifications. a tool (configurator) for generating the nucleus of the rx78k/0 and multiple information tables is supplied. used in combination with an assembler package (ra78k/0) and device file (df780148) (both sold separately). the real-time os is a dos-based application. it should be used in the dos prompt when using it in windows. rx78k/0 real-time os part number: s rx78013- ???? caution to purchase the rx78k/0, first fill in the purchase application form and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx78013- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 windows (japanese version) note bb13 ibm pc/at compatibles windows (english version) note 3.5-inch 2hd fd 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4), solaris (rel. 2.5.1) 1/4-inch cgmt note can also be operated in dos environment.
preliminary user?s manual u15947ej1v1ud 551 appendix c register index c.1 register index (in alphabetical order with respect to register names) [a] a/d conversion result register (adcr) ? 259 a/d converter mode register (adm) ? 261 analog input channel specification register (ads) ? 263 asynchronous serial interface control register 6 (asicl6) ? 314, 321 asynchronous serial interface operation mode register 0 (asim0) ? 282, 286, 287 asynchronous serial interface operation mode register 6 (asim6) ? 308, 316, 317 asynchronous serial interface reception error status register 0 (asis0) ? 284, 289 asynchronous serial interface reception error status register 6 (asis6) ? 310, 319 asynchronous serial interface transmission status register 6 (asif6) ? 311, 320 automatic data transfer address count register 0 (adtc0) ? 370 automatic data transfer address point specification register 0 (adtp0) ? 375, 391 automatic data transfer interval specification register 0 (adti0) ? 377, 392 [b] baud rate generator control register 0 (brgc0) ? 285, 296 baud rate generator control register 6 (brgc6) ? 313, 338 [c] capture/compare control register 00 (crc00) ? 166 capture/compare control register 01 (crc01) ? 166 clock monitor mode register (clm) ? 467 clock selection register 6 (cksr6) ? 312, 337 clock output selection register (cks) ? 253 [d] divisor selection register 0 (brgca0) ? 375, 382, 390 [e] 8-bit timer compare register 50 (cr50) ? 199 8-bit timer compare register 51 (cr51) ? 199 8-bit timer counter 50 (tm50) ? 199 8-bit timer counter 51 (tm51) ? 199 8-bit timer h carrier control register 1 (tmcyc1) ? 218 8-bit timer h compare register 00 (cmp00) ? 215 8-bit timer h compare register 01 (cmp01) ? 215 8-bit timer h compare register 10 (cmp10) ? 215 8-bit timer h compare register 11 (cmp11) ? 215 8-bit timer h mode register 0 (tmhmd0) ? 215 8-bit timer h mode register 1 (tmhmd1) ? 215 8-bit timer mode control register 50 (tmc50) ? 202 8-bit timer mode control register 51 (tmc51) ? 202
appendix c register index preliminary user?s manual u15947ej1v1ud 552 external interrupt falling edge enable register (egn) ? 437 external interrupt rising edge enable register (egp) ? 437 [i] input switch control register (isc) ? 120 internal expansion ram size switching register (ixs) ? 492 internal memory size switching register (ims) ? 491 interrupt mask flag register 0h (mk0h) ? 435 interrupt mask flag register 0l (mk0l) ? 435 interrupt mask flag register 1h (mk1h) ? 435 interrupt mask flag register 1l (mk1l) ? 435 interrupt request flag register 0h (if0h) ? 434 interrupt request flag register 0l (if0l) ? 434 interrupt request flag register 1h (if1h) ? 434 interrupt request flag register 1l (if1l) ? 434 [k] key return mode register (krm) ? 447 [l] low-voltage detection level selection register (lvis) ? 479 low-voltage detection register (lvim) ? 477 [m] main osc control register (moc) ? 139 main clock mode register (mcm) ? 138 memory expansion mode register (mem) ? 125 memory expansion wait setting register (mm) ? 126 multiplier/divider control register 0 (dmuc0) ? 417 multiplication/division data register a0 (mda0h, mda0l) ? 415 multiplication/division data register b0 (mdb0) ? 416 [o] oscillation stabilization time counter status register (ostc) ? 139, 450 oscillation stabilization time select register (osts) ? 140, 451 [p] port 0 (p0) ? 91 port 1 (p1) ? 95 port 12 (p12) ? 110 port 13 (p13) ? 111 port 14 (p14) ? 112 port 2 (p2) ? 101 port 3 (p3) ? 102 port 4 (p4) ? 104 port 5 (p5) ? 105 port 6 (p6) ? 106 port 7 (p7) ? 109
appendix c register index preliminary user?s manual u15947ej1v1ud 553 port mode register 0 (pm0) ? 116, 173 port mode register 1 (pm1) ? 116, 204 port mode register 12 (pm12) ? 116 port mode register 14 (pm14) ? 116, 255 port mode register 3 (pm3) ? 116, 204 port mode register 4 (pm4) ? 116 port mode register 5 (pm5) ? 116 port mode register 6 (pm6) ? 116 port mode register 7 (pm7) ? 116 power-fail comparison mode register (pfm) ? 264 power-fail comparison threshold register (pft) ? 264 prescaler mode register 00 (prm00) ? 170 prescaler mode register 01 (prm01) ? 170 priority specification flag register 0h (pr0h) ? 436 priority specification flag register 0l (pr0l) ? 436 priority specification flag register 1h (pr1h) ? 436 priority specification flag register 1l (pr1l) ? 436 processor clock control register (pcc) ? 135 pull-up resistor option register 0 (pu0) ? 119 pull-up resistor option register 1 (pu1) ? 119 pull-up resistor option register 12 (pu12) ? 119 pull-up resistor option register 14 (pu14) ? 119 pull-up resistor option register 3 (pu3) ? 119 pull-up resistor option register 4 (pu4) ? 119 pull-up resistor option register 5 (pu5) ? 119 pull-up resistor option register 6 (pu6) ? 119 pull-up resistor option register 7 (pu7) ? 119 [r] receive buffer register 0 (rxb0) ? 281 receive buffer register 6 (rxb6) ? 307 receive shift register 0 (rxs0) ? 281 receive shift register 6 (rxs6) ? 307 remainder data register 0 (sdr0) ? 415 reset control flag register (resf) ? 465 ring-osc mode register (rcm) ? 137 [s] serial i/o shift register 0 (sioa0) ? 370 serial i/o shift register 10 (sio10) ? 347 serial i/o shift register 11 (sio11) ? 347 serial clock selection register 10 (csic10) ? 350, 356 serial clock selection register 11 (csic11) ? 350, 356 serial operation mode register 10 (csim10) ? 347, 352, 353 serial operation mode register 11 (csim11) ? 347, 352, 353 serial operation mode specification register 0 (csima0) ? 370, 378, 379, 387 serial status register 0 (csis0) ? 372, 380, 388 serial trigger register 0 (csit0) ? 374, 390
appendix c register index preliminary user?s manual u15947ej1v1ud 554 16-bit timer capture/compare register 000 (cr000) ? 161 16-bit timer capture/compare register 001 (cr001) ? 161 16-bit timer capture/compare register 010 (cr010) ? 162 16-bit timer capture/compare register 011 (cr011) ? 162 16-bit timer counter 00 (tm00) ? 161 16-bit timer counter 01 (tm01) ? 161 16-bit timer mode control register 00 (tmc00) ? 163 16-bit timer mode control register 01 (tmc01) ? 163 16-bit timer output control register 00 (toc00) ? 167 16-bit timer output control register 01 (toc01) ? 167 [t] timer clock selection register 50 (tcl50) ? 200 timer clock selection register 51 (tcl51) ? 200 transmit buffer register 10 (sotb10) ? 346 transmit buffer register 11 (sotb11) ? 346 transmit buffer register 6 (txb6) ? 307 transmit shift register 0 (txs0) ? 281 transmit shift register 6 (txs6) ? 307 [w] watchdog timer enable register (wdte) ? 246 watchdog timer mode register (wdtm) ? 244 watch timer operation mode register (wtm) ? 237
appendix c register index preliminary user?s manual u15947ej1v1ud 555 c.2 register index (in alphabetical order with respect to register symbol) [a] adcr: a/d conversion result register ? 259 adm: a/d converter mode register ? 261 ads: analog input channel specification register ? 263 adtc0: automatic data transfer address count register 0 ? 370 adti0: automatic data transfer interval specification register 0 ? 377, 392 adtp0: automatic data transfer address point specification register 0 ? 375, 391 asicl6: asynchronous serial interface control register 6 ? 314, 321 asif6: asynchronous serial interface transmission status register 6 ? 311, 320 asim0: asynchronous serial interface operation mode register 0 ? 282, 286, 287 asim6: asynchronous serial interface operation mode register 6 ? 308, 316, 317 asis0: asynchronous serial interface reception error status register 0 ? 284, 289 asis6: asynchronous serial interface reception error status register 6 ? 310, 319 [b] brgca0: divisor selection register 0 ? 375, 382, 390 brgc0: baud rate generator control register 0 ? 285, 296 brgc6: baud rate generator control register 6 ? 313, 338 [c] cks : clock output selection register ? 253 cksr6: clock selection register 6 ? 312, 337 clm: clock monitor mode register ? 467 cmp00: 8-bit timer h compare register 00 ? 215 cmp01: 8-bit timer h compare register 01 ? 215 cmp10: 8-bit timer h compare register 10 ? 215 cmp11: 8-bit timer h compare register 11 ? 215 cr000: 16-bit timer capture/compare register 000 ? 161 cr001: 16-bit timer capture/compare register 001 ? 161 cr010: 16-bit timer capture/compare register 010 ? 162 cr011: 16-bit timer capture/compare register 011 ? 162 cr50: 8-bit timer compare register 50 ? 199 cr51: 8-bit timer compare register 51 ? 199 crc00: capture/compare control register 00 ? 166 crc01: capture/compare control register 01 ? 166 csic10: serial clock selection register 10 ? 350, 356 csic11: serial clock selection register 11 ? 350, 356 csim10: serial operation mode register 10 ? 347, 352, 353 csim11: serial operation mode register 11 ? 347, 352, 353 csima0: serial operation mode specification register 0 ? 370, 378, 379, 387 csis0: serial status register 0 ? 372, 380, 388 csit0: serial trigger register 0 ? 374, 390 [d] dmuc0: multiplier/divider control register 0 ? 417
appendix c register index preliminary user?s manual u15947ej1v1ud 556 [e] egn: external interrupt falling edge enable register ? 437 egp: external interrupt rising edge enable register ? 437 [i] if0h: interrupt request flag register 0h ? 434 if0l: interrupt request flag register 0l ? 434 if1h: interrupt request flag register 1h ? 434 if1l: interrupt request flag register 1l ? 434 ims: internal memory size switching register ? 491 isc: input switch control register ? 120 ixs: internal expansion ram size switching register ? 492 [k] krm: key return mode register ? 447 [l] lvim: low-voltage detection register ? 477 lvis: low-voltage detection level selection register ? 479 [m] mcm: main clock mode register ? 138 mda0h: multiplication/division data register a0 ? 415 mda0l: multiplication/division data register a0 ? 415 mdb0: multiplication/division data register b0 ? 416 mem: memory expansion mode register ? 125 mk0h: interrupt mask flag register 0h ? 435 mk0l: interrupt mask flag register 0l ? 435 mk1h: interrupt mask flag register 1h ? 435 mk1l: interrupt mask flag register 1l ? 435 mm: memory expansion wait setting register ? 126 moc: main osc control register ? 139 [o] ostc: oscillation stabilization time counter status register ? 139, 450 osts: oscillation stabilization time select register ? 140, 451 [p] p0: port 0 ? 91 p1: port 1 ? 95 p12: port 12 ? 110 p13: port 13 ? 111 p14: port 14 ? 112 p2: port 2 ? 101 p3: port 3 ? 102 p4: port 4 ? 104 p5: port 5 ? 105 p6: port 6 ? 106
appendix c register index preliminary user?s manual u15947ej1v1ud 557 p7: port 7 ? 109 pcc: processor clock control register ? 135 pfm: power-fail comparison mode register ? 264 pft: power-fail comparison threshold register ? 264 pm0: port mode register 0 ? 116, 173 pm1: port mode register 1 ? 116, 204 pm12: port mode register 12 ? 116 pm14: port mode register 14 ? 116, 255 pm3: port mode register 3 ? 116, 204 pm4: port mode register 4 ? 116 pm5: port mode register 5 ? 116 pm6: port mode register 6 ? 116 pm7: port mode register 7 ? 116 pr0h: priority specification flag register 0h ? 436 pr1h : priority specification flag register 1h ? 436 pr0l: priority specification flag register 0l ? 436 pr1l: priority specification flag register 1l ? 436 prm00: prescaler mode register 00 ? 170 prm01: prescaler mode register 01 ? 170 pu0: pull-up resistor option register 0 ? 119 pu1: pull-up resistor option register 1 ? 119 pu12: pull-up resistor option register 12 ? 119 pu14: pull-up resistor option register 14 ? 119 pu3: pull-up resistor option register 3 ? 119 pu4: pull-up resistor option register 4 ? 119 pu5: pull-up resistor option register 5 ? 119 pu6: pull-up resistor option register 6 ? 119 pu7: pull-up resistor option register 7 ? 119 [r] rcm: ring-osc mode register ? 137 resf: reset control flag register ? 465 rxb0: receive buffer register 0 ? 281 rxb6: receive buffer register 6 ? 307 rxs0: receive shift register 0 ? 281 rxs6: receive shift register 6 ? 307 [s] sdr0: remainder data register 0 ? 415 sio10: serial i/o shift register 10 ? 347 sio11: serial i/o shift register 11 ? 347 sioa0: serial i/o shift register 0 ? 370 sotb10: transmit buffer register 10 ? 346 sotb11: transmit buffer register 11 ? 346 [t] tcl50: timer clock selection register 50 ? 200 tcl51: timer clock selection register 51 ? 200
appendix c register index preliminary user?s manual u15947ej1v1ud 558 tm00: 16-bit timer counter 00 ? 161 tm01: 16-bit timer counter 01 ? 161 tm50: 8-bit timer counter 50 ? 199 tm51: 8-bit timer counter 51 ? 199 tmc00: 16-bit timer mode control register 00 ? 163 tmc01: 16-bit timer mode control register 01 ? 163 tmc50: 8-bit timer mode control register 50 ? 202 tmc51: 8-bit timer mode control register 51 ? 202 tmcyc1: 8-bit timer h carrier control register 1 ? 218 tmhmd0: 8-bit timer h mode register 0 ? 215 tmhmd1: 8-bit timer h mode register 1 ? 215 toc00: 16-bit timer output control register 00 ? 167 toc01: 16-bit timer output control register 01 ? 167 txb6: transmit buffer register 6 ? 307 txs0: transmit shift register 0 ? 281 txs6: transmit shift register 6 ? 307 [w] wdte: watchdog timer enable register ? 246 wdtm: watchdog timer mode register ? 244 wtm : watch timer operation mode register ? 237
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